PCI2040 datasheet(20/79 Pages) TI

20 / 79 page

2–8

Table 2–7. Compact PCI Hot Swap Interface

TERMINAL

NAME

NO.

I/O

DESCRIPTION

NAME

PGE

GGU

I/O

DESCRIPTION

HSENUM

N12

Hot swap ENUM. This is an active low open drain signaling output that is asserted when either bit 7 (INS)

or bit 6 (EXT) are set and bit 1 (EIM) is cleared in the CPCI hot swap control and status register (see

Section 4.35). This output indicates to the system that an insertion event occurred or that a removal event

is about to occur.

HSLED

M12

Hot swap LED. This output is controlled via bit 3 (LOO) in the CPCI hot swap control and status register

(see Section 4.35) and is provided to indicate when a hot-swap device is about to be removed. When

PCI_RST is asserted to PCI2040, it drives this LED output until the serial ROM has completed preload

and the ejector switch has been closed indicated by the HSSWITCH input.

HSSWITCH

N13

Hot swap handle switch. This input provides status of the ejector handle state and is used in the bit 7 (INS)

and bit 6 (EXT) logic in the CPCI hot swap control and status register (see Section 4.35). The status of

HSSWITCH is not directly read via CPCI hot swap control and status register but can be read through bit 8

(HSSWITCH_STS) in the miscellaneous control register (see Section 4.26).

Table 2–8. General-Purpose Bus Interface

TERMINAL

NAME

NO.

I/O

DESCRIPTION

NAME

PGE

GGU

I/O

DESCRIPTION

GPD15

GPD14

GPD13

GPD12

GPD11

GPD10

GPD9

GPD8

GPD7

GPD6

GPD5

GPD4

GPD3

GPD2

GPD1

GPD0

100

E10

E11

E12

E13

F10

F12

F13

G10

G13

G12

H13

H11

H10

J13

J12

J11

I/O

GP data bus. 16-bit data bus.

GPA5

GPA4

GPA3

GPA2

GPA1

GPA0

106

107

108

109

110

111

C11

B13

B12

A13

A12

B11

I/O

GP address lines. 6-bit address bus.

GP_CS

112

A11

GP chip select

GP_INT

M13

I/O

GP interrupt. Interrupt from a device on the GP bus.

GP_RD

130

I/O

GP read.

GP_RDY

L12

I/O

GP ready. Whenever the device on the GP bus is ready to accept a read or write from PCI2040, GP_RDY

is asserted. GP_RDY is deasserted when the device is in recovery from a read or write operation.

GP_RST

L11

GP reset. An active low output that will follow the state of GRST.

GP_WR

129

I/O

GP write.

PCI2040 Datasheet(PDF) 20 Page - Texas Instruments

PCI2040 Datasheet(HTML) 20 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL