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PCI2040 Datasheet(PDF) 53 Page - Texas Instruments |
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PCI2040 Datasheet(HTML) 53 Page - Texas Instruments |
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53 / 79 page ![]() 5–1 5 HPI Control and Status Registers This section covers the PCI2040 HPI control and status register (HPI CSR) space. The PCI2040 allows software to access the HPI configuration through either memory or I/O address space. The memory base address is programmable via the HPI CSR base address register (PCI offset 10h). The I/O base address is programmable via the HPI CSR I/O base address register (PCI offset 58h). Table 5–1. HPI Configuration Register Map REGISTER NAME OFFSET Interrupt event set 00h Interrupt event clear 04h Interrupt mask set 08h Interrupt mask clear 0Ch Reserved HPI error report 10h HPI DSP implementation HPI reset 14h Reserved HPI data width 18h |
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