PCI2040 datasheet(30/79 Pages) TI

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3–10

and bit 1 (EIM). Since no HSSWITCH status is provided in the CPCI hot swap control and status register, PCI2040

provides bit 8 (HSSWITCH_STS) in the miscellaneous control register (see Section 4.26).

HSENUM is an active low open drain output that is asserted when either bit 7 (INS) or bit 6 (EXT) are set and bit 1

(EIM, the HSENUM mask bit) is cleared. For the insertion event, PCI2040 will drive HSLED after PCI_RST until the

serial ROM preload is complete and the ejector handle is closed (HSSWITCH_STS is 0). When these conditions are

met, the HSLED is under software control via bit 3 (LOO). Bit 7 (INS) is set when the conditions described above are

met and bit 6 (EXT) is 0. Thus, bit 7 (INS) is set following an insertion when the board implementing PCI2040 is ready

for configuration and cannot be set by software.

For the removal event, bit 6 (EXT) is set when the ejector handle is opened (HSSWITCH_STS is 1) and bit 7 (INS)

is 0. This will cause HSENUM to be asserted if bit 1 (EIM) is 0, and software will halt connection with PCI2040 and

light the LED via bit 3 (LOO). The board may then be safely removed.

See the

Compact PCI Hot Swap Specification PICMG 2.1 for more details.

3.10 General-Purpose Bus

This section discusses the general-purpose interface of PCI2040. This is a 16-bit data and a 6-bit address bus. The

6-bit address bus is mapped directly to PCI address bits 7–2. This means that each address on the GP bus

corresponds to a 32-bit (1 DW) address on the PCI bus for a total of 256 bytes of addressable space. Because the

GP bus is only a 16-bit data bus, only the lower 16 bits (15–0) of the PCI data bus is used. In other words, the only

valid byte enable combination is 1100b.

The general-purpose bus read/write strobes must default to the JTAG TBC (8990) timing requirements. However,

GP_RDY signal can be used to extend the use of the bus for slower devices.

Most of the GP bus signals are multiplexed onto the HPI bus as described in the table below. In addition to the

multiplexed signals, there are three dedicated GP bus signals which are GPINT, GPRDY, and GPRST.

Table 3–4. General-Purpose Bus Signals

HPI SIGNALS

GP BUS SIGNALS

TYPE

NOTES

HAD15–HAD0

GP_DATA15–GP_DATA0

I/O

GP data bus. A 16-bit data bus

HBE0

GPA0

One of the six address lines

HBE1

GPA1

One of the six address lines

HWIL

GPA2

One of the six address lines

HCNTL0

GPA3

One of the six address lines

HCNTL1

GPA4

One of the six address lines

HR/W

GPA5

One of the six address lines

HDS

GP_CS

GP chip select. This signal is asserted during an access on the GP bus.

GPIO5

GP_RD

GP read strobe. This active low signal indicates a read from a device on the bus. The

data on the bus is valid on the rising edge of GP_RD.

GPIO4

GP_WR

GP write strobe. This active low signal indicates a write to a device on the bus. The

data on the bus is valid on the rising edge of GP_WR.

Terminal 74

GP_INT

GP interrupt. Interrupt from a device on the GP bus.

Terminal 75

GP_RDY

GP ready. Whenever the device on the GP bus is ready to accept a read or write from

PCI2040, GP_RDY is asserted. RDY is deasserted when the device is in recovery

from a read or write operation.

Terminal 70

GP_RST

GP reset. An active low output that follows the state of GRST.

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