PCI2040 datasheet(69/79 Pages) TI

69 / 79 page

6–11

Table 6–4. C6X HPI Control Register

BIT

FIELD NAME

HOST TYPE

DSP TYPE

FUNCTION

31–21

RSVD

Reserved. Bits 31–21 return 0s when read.

FETCH

Host fetch request. The value read by the host or the CPU is always 0. Only host can write

to this register. When host writes 1 to this bit, it requests a fetch into HPI data register of

the word at the word pointed to by HPI address register. Note that the value of 1 is never

actually written to this bit.

HRDY

Ready signal to host. It is not masked by the HCS as the HRDY pin is.

0 = Host is busy; the internal bus is waiting for an HPI data request to finish.

1 = Host is ready to transfer data

HINT

DSP-to-host interrupt. The inverted value of this bit determines the state of the HINT

output.

DSPINT

Host-to-DSP interrupt.

HWOB

HWOB affects both data and address transfers. Only the host can modify this bit and it is

read-only to the DSP. HWOB must be initialized before the first data or address register

access.

0 = First byte is the MS

1 = First byte is the LS

15–5

RSVD

Reserved. Bits 15–5 return 0s when read.

FETCH

Host fetch request. The value read by the host or the CPU is always is 0. Only host can

write to this register. When host writes 1 to this bit, it requests a fetch into HPI data register

of the word at the word pointed to by HPI address register. Note that the value of 1 is never

actually written to this bit.

HRDY

Ready signal to host. It is not masked by the HCS as the HRDY pin is.

0 = Host is busy; the internal bus is waiting for an HPI data request to finish.

1 = Host is ready to transfer data

HINT

DSP-to-host interrupt. The inverted value of this bit determines the state of the HINT

output.

DSPINT

Host-to-DSP interrupt.

HWOB

HWOB affects both data and address transfers. Only the host can modify this bit and it is

read-only to the DSP. HWOB must be initialized before the first data or address register

access.

0 = First byte is the MS

1 = First byte is the LS

6.3.6

Software Handshaking Using HRDY and FETCH

Software handshaking using HRDY and FETCH bits in the HPI control register is a C6x feature not supported in

PCI2040 because it will support HRDY pin from DSP to host for insertion of wait states.

PCI2040 Datasheet(PDF) 69 Page - Texas Instruments

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