PCI2040 datasheet(23/79 Pages) TI

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3–3

•

Diagnostic register – Diagnostic

•

HPI DSP implementation register – HPI_Imp Byte 0

•

HPI data width register – HPI_DW Byte 0

SubClass

BaseClass

SubSys Byte 0

SubSys Byte 1

SubSys Byte 2

SubSys Byte 3

GPIO Select

RSVD

Misc Ctrl Byte 0

Misc Ctrl Byte 1

Diagnostic

HPI_Imp Byte 0

RSVD

HPI_DW Byte 0

RSVD

Word Address 0

Word Address 1

Word Address 2

Word Address 3

Word Address 4

Word Address 5

Word Address 6

Word Address 7

Word Address 8

Word Address 9

Word Address 10

Word Address 11

Word Address 12

Word Address 13

Word Address 14

Word Address 15

RSVD

RSVD_DIAG

Word Address 16 (10h)

Word Address 17

Word Address 18

Word Address 19

Word Address 20

Word Address 21

Word Address 22

Word Address 23

Word Address 24

Word Address 25

Word Address 26

Word Address 27

Word Address 28

Word Address 29

Word Address 30

Word Address 31

...AVAIL...

Figure 3–2. PCI2040 Serial ROM Data Format

When PCI2040 accesses an implemented serial ROM, it always addresses the serial ROM at slave address

8’b10100000. The serial ROM data format described above utilizes 32 bytes of address space, some of which are

reserved for future generations of the PCI2040. A byte at address 31 is reserved for diagnostic software purposes

and will not be allocated to future generations of the PCI2040. Serial ROM addresses above word address 31 are

available for use by PCI2040 applications. If the data at word address 0 is FFh, then the PCI2040 will stop reading

from the serial ROM. This feature prevents the uninitialized data from being loaded into the PCI2040’s registers.

3.5

PCI2040 Host Port Interface

The PCI2040 HPI interface is used to access TI’s TMS320C54X or TMS320C6X DSP chips. The devices connected

to the HPI interface are memory-mapped in host memory. The host system processor accesses the HPI interface

via slave accesses to PCI2040. The DSP devices can generate interrupts, and the PCI2040 passes these interrupt

requests to the PCI bus via INTA. See Section 3.7,

Interrupts, for more information on PCI2040 interrupts.

The HPI port on DSP devices is a parallel port that allows access to the DSP’s memory space and internal registers.

The PCI2040 has to configure the HPI interface on the DSP by accessing the DSP’s HPI control register (HPIC). Other

DSP HPI registers include the HPI data register (HPID) and the HPI address register (HPIA). See Section 6,

DSP

HPI Overview for more information on DSP registers.

3.5.1

Identifying Implemented Ports and DSP Types

The PCI2040 supports up to four DSPs of both the C54x and C6x types. It may be useful for generic software to

discover what number and type of DSPs are connected to the PCI2040. This is accomplished by using the HPI DSP

implementation register (see Section 5.5) and HPI data width register (see Section 5.6) in the HPI control and status

outputs are connected, and the HPI data width register identifies whether the HPI port per connected DSP is 8 bits

(C54x) or 16 bits (C6x).

PCI2040 Datasheet(PDF) 23 Page - Texas Instruments

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