PCI2040 datasheet(28/79 Pages) TI

28 / 79 page

3–8

3.8.1

PCI Power Management Register Interface

PCI2040 is

PCI Bus Power Interface Management Specification Revision 1.0 and 1.1 compliant. By default, PCI2040

provides the PCI power management PM 1.0 register set which is documented in Section 4.30. PCI2040 may be

programmed to provide a PCI PM 1.1 register set by setting bit 4 (PM11_EN) of the miscellaneous control register

to 1 (see Section 4.26).

The PCI power management register changes required to provide PCI PM 1.1 compliance to the power management

capabilities register (see Section 4.30) are summarized in Table 3–3.

Table 3–3. PMC Changes for PCI PM 1.1 Register Model

BIT

FIELD NAME

TYPE

DESCRIPTION

15–9

PM 1.0 Compliant

Same as PM 1.0 Implementation. No change.

8–6

Aux_Current

Aux_Current.

This

field

reports

the

Vaux requirements for PCI2040. If bit 15

(D3cold_PMESupport) in the power management capabilities register is set (see Section 4.30),

then this field returns 3’b001 indicating that PCI2040 draws a maximum of 55 mA while

programmed to D3. If bit 15 (D3cold_PMESupport) is 0, then this field returns 3’b000 since no

wake from D3cold is supported.

Bit 6 is aliased to bit 15 and is read-only.

PM 1.0 Compliant

Same as PM 1.0 Implementation. No change.

RSVD

This reserved field returns 0 when read in the PCI PM 1.1 register model and returns 1 when

read in the PCI PM 1.0 model.

PM 1.0 Compliant

Same as PM 1.0 Implementation. No change.

2–0

Version

These three bits return 010b when read, indicating that there are 4 bytes of general-purpose

power management (PM) registers as described in the draft revision 1.1

PCI Bus Power

Management Interface Specification.

3.8.2

PCI Power Management Device States and Transitions

PCI2040 supports all D0–D3 device power states, and can assert PME from any power state including D3cold when

Vaux is supplied. The PCI2040’s power state implementation is simply disabling the HPI state machine when in the

D1, D2, or D3 power states. D0 is the fully operational power state.

If an HPI cycle initiated by PCI2040 is in progress when bits 1 and 0 (PWRSTATE field) in the power management

control/status register are programmed to D1, D2, or D3 (see Section 4.31), then the PCI2040 will complete the cycle

in progress before transitioning to the lower power state.

On a transition to the D0 power state from the D3 power state, PCI2040 asserts an internal signal equivalent to a

PCI_RST which does not reset all internal states. There are several register bits that are reset by GRST versus the

PCI_RST, and these are referred to as the PME context (or sometimes sticky) bits.

The PME context bits for PCI2040 are listed below and Figure 3–3 illustrates the relationship between the PME

context bits: GRST, and PCI_RST. The addition of GRST allows for retaining device state from a D3 to D0 transition

when the PCI interface may transition from B3 to B0 and issue a PCI reset.

PCI2040 PME context bits for PCI space:

•

0x0A – SubClass Code register (all implemented bits)

•

0x0B – BaseClass Code register (all implemented bits)

•

0x2C – Subsystem vendor ID register (all implemented bits)

•

0x2E – Subsystem ID register (all implemented bits)

•

0x44 – GPIO select register (all implemented bits)

•

0x46 – GPIO direction control register (all implemented bits)

•

0x47 – GPIO output data register (all implemented bits)

PCI2040 Datasheet(PDF) 28 Page - Texas Instruments

PCI2040 Datasheet(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL