PCI2040 datasheet(70/79 Pages) TI

70 / 79 page

6–12

6.3.7

Host Access Sequence

The host access sequence in C6x is similar to C54x except for the HPI data register write. The host begins accessing

HPI by initializing the HPI control register, then by initializing the HPI address register, and then by writing data to or

reading data from the HPI data register. Reading or writing to the HPI data register initiates an internal cycle that

transfers the desired data between the HPI data register and DMA auxiliary channel. Typically, host does not break

the first half-word/second half-word sequence. If this sequence is broken, then the data is lost. During the HPI data

Byte

Enables (HBE0 and HBE1), for more details.

6.3.8

Single Half-Word Cycles

In the normal operation, every transfer must consist of two half-word accesses. However, to speed the operation, the

C6x allows single half-word accesses. The PCI2040 does not support the half-word cycles.

6.3.9

Memory Access Through HPI During Reset

During the reset, when HCS is active low and HRDY is inactive high, and vice versa, the HPI can not be used but

certain boot modes can allow the host to write to the CPU’s memory space including configuring the EMIF

configuration registers to define external memory before accessing it. Note that the device is not in reset during these

boot modes but the CPU itself is in reset until the boot completes.

6.3.10 Examples of Transactions Targeting the C6X

The following two figures depict typical transactions on the HPI bus which are targeting a C6X. Both of these figures

are very similar with one being a write transaction and the other being a read transaction. Because both transactions

are similar, the following event flow can be used to describe both transactions.

The host port is idle.

HCNTL0 and HCNTL1 are driven high indicating to the C6X that this transaction is going to target the HPID

w/o auto-increment enabled. The HR/W is driven low indicating to the C6X that this transaction is a write.

HCS0 is asserted indicating that this transaction is targeting DSP0. The first two bytes or half–word is driven

onto the HAD bus. Both HBE1 and HBE0 are driven low. Also during clock 3 the HDS is asserted. During

this time, the C6X will latch the values of HCNTL1, HCNTL0, HWIL, and HR/W.

The PCI2040 will sample the state of HRDY6X0. If the C6X indicates it is not ready, then the PCI2040 will

wait until the C6X indicates it is ready before it deasserts HDS and HWIL.

Because the state of the HRDY6X0 signal indicates the C6X is ready, the PCI2040 deasserts HDS. The

C6X latches the data, BBAAh, on the rising edge of HDS. The HWIL is driven high. The C6X also latches

the value of HBE1 and HBE0. In this example, both these signals are low indicating to the C6X that both

bytes of the half-word are valid.

Same as Step 3.

Same as Step 4.

Same as Step 5 except HCS0 is deasserted indicating the transaction has completed.

PCI2040 Datasheet(PDF) 70 Page - Texas Instruments