PCI2040 datasheet(45/79 Pages) TI

45 / 79 page

4–13

4.22 GPIO Input Data Register

The GPIO input data register reflects the state of the GPIO pins, and defaults to an unknown value.

Bit

Name

GPIO input data

Type

Default

GPIO input data

Type:

Read-only

Offset:

45h

Default:

XXh

Table 4–9. GPIO Input Data Register

BIT

FIELD NAME

TYPE

DESCRIPTION

7–6

RSVD

Reserved. Bits 7 and 6 return 0s when read.

5–0

GPIO[5:0] Pin State

GPIO5–GPIO0 pin state. Returns the logical value of the data input to the GPIO5–GPIO0 terminals.

4.23 GPIO Direction Control Register

The GPIO direction control register controls the direction of GPIO pins.

Bit

Name

GPIO direction control

Type

Default

GPIO direction control

Type:

Read-only, Read/Write

Offset:

46h

Default:

00h

Table 4–10. GPIO Direction Control Register

BIT

FIELD NAME

TYPE

DESCRIPTION

7–6

RSVD

Reserved. Bits 7 and 6 return 0s when read.

5–0

GPIO[5:0] Direction

Control

GPIO5–GPIO0 direction control. When the GPIOn direction control bit is set, then the GPIOn signal

is an output. When the GPIOn direction control bit is 0, the GPIOn signal is an input.

PCI2040 Datasheet(PDF) 45 Page - Texas Instruments

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