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PCI2040 Datasheet(PDF) 17 Page - Texas Instruments

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Part # PCI2040
Description  PCI2040 PCI-DSP Bridge controller
PDF  79 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCI2040 Datasheet(HTML) 17 Page - Texas Instruments

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2–5
Table 2–4. PCI System Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
PGE
GGU
I/O
DESCRIPTION
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
1
2
3
4
6
7
8
9
14
15
16
17
23
24
25
26
44
45
46
47
48
52
53
54
58
59
60
61
62
64
65
66
A1
B1
C2
C1
D3
D2
D1
E4
F3
F2
F1
G2
H3
H4
J1
J2
N4
K5
L5
M5
N5
N6
M7
N7
M8
L8
K8
N9
M9
K9
N10
M10
I/O
32-bit multiplexed address/data bus
PCI_C/BE3
PCI_C/BE2
PCI_C/BE1
PCI_C/BE0
11
28
42
56
E2
J4
L4
K7
I
PCI command and byte enable
PCI_PCLK
21
H1
I
PCI clock. Provides timing for all PCI transactions with a maximum frequency of 33 MHz.
PCI_DEVSEL
33
L2
O
Device select
PCI_FRAME
29
K1
I
PCI cycle frame
PCI_IDSEL
12
E1
I
Initialization and device select
PCI_INTA
50
L6
O
Interrupt A. INTA indicates to the host that PCI2040 requires attention.
PCI_IRDY
30
K2
I
Initiator ready
PCI_LOCK
41
K4
I
PCI lock
PCI_PAR
39
M3
I/O
PCI parity
PCI_PERR
37
N1
I/O
Parity error
PCI_RST
19
G3
I
PCI reset. Assertion forces PCI2040 non-PME context to a predetermined state.
PCI_SERR
38
N2
O
System error
PCI_STOP
34
L3
O
PCI stop
PCI_TRDY
32
L1
O
Target ready



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