PCI2040 datasheet(19/79 Pages) TI

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Table 2–6. Host Port Interface Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

NAME

PGE

GGU

I/O

DESCRIPTION

HAD15

HAD14

HAD13

HAD12

HAD11

HAD10

HAD9

HAD8

HAD7

HAD6

HAD5

HAD4

HAD3

HAD2

HAD1

HAD0

100

E10

E11

E12

E13

F10

F12

F13

G10

G13

G12

H13

H11

H10

J13

J12

J11

I/O

Data. A 16-bit parallel, bidirectional, and 3-state data bus used to access registers on external

devices controlled by PCI2040. HAD15 is MSB and HAD0 is LSB.

HR/W/GPA5

106

C11

Read/Write. The PCI2040 drives this signal to 0 on a host port interface for a write and to 1

on a host port interface for a read.

HDS/GP_CS

112

A11

Read strobe/data strobe. Active low signal that controls the transfer of data during an HPI

cycle, and indicates to the DSP that the data on HAD15–HAD0 is valid. This signal must be

connected to HDS1 or HDS2 on the DSP. Unused DSP HDSx inputs must be tied high.

HINT3

HINT2

HINT1

HINT0

K13

K12

K11

L13

HPI Interrupts. These four interrupts from the DSPs are connected point-to-point between

PCI2040 and each implemented DSP. The PCI2040 may be programmed to assert a PCI

interrupt when the DSPs assert any HINT3–HINT0. From the DSP perspective, these signals

are controlled by the HINT bit in the HPI control register and are driven high when the DSPs

are being reset (and placed in high impedance when EMU1/OFF is asserted).

HBE1/GPA1

HBE0/GPA0

110

111

A12

B11

Byte enables. These active low signals are only used when communicating with the C6x DSP.

They indicate which bytes of the data bus are valid when writing to the C6x HPI data register

and are not meaningful in any other conditions.

HWIL/GPA2

109

A13

Half-word identification select. Identifies first or second half-word of transfer. HWIL is low for

the first half-word and high for the second half-word. This is not to be confused with the BOB

bit in the DSP HPI control register which controls MSB/LSB from the DSP perspective.

HCNTL1/GPA4

HCNTL0/GPA3

107

108

B13

B12

Control signals for DSP access mode. Selects an access to DSP HPI address register, HPI

control register, or HPI data register (and controls auto-increment). The HCNTL1 and HCNTL0

combinations are different for C54x and C6x DSPs.

HCS3

HCS2

HCS1

HCS0

105

104

103

102

C12

C13

D11

D12

Chip selects. These four chip selects to the DSPs are connected point-to-point between

PCI2040 and each implemented DSP. The input to the DSP serves as an enable input for the

HPI and must be low during an access and may stay low between accesses.

HRDY5x3/HRDY6x3

HRDY5x2/HRDY6x2

HRDY5x1/HRDY6x1

HRDY5x0/HRDY6x0

122

121

120

119

Host ready signals. These ready signals from the DSPs are connected point-to-point between

PCI2040 and each implemented DSP. This ready signal is active high for C54x DSPs and

active low for C6x DSPs. When asserted, it indicates that the DSP is ready for a transfer to

be performed, and is deasserted when the DSP is busy completing the internal portion of the

previous transaction. HCS enables HRDY for the DSP; that is, HRDY is always asserted when

the chip selects are deasserted. The DSP places this ready signal in high impedance when

EMU1/OFF is active (low).

HRST3

HRST2

HRST1

HRST0

117

116

115

114

A10

B10

C10

Host-to-DSP resets. These active low reset signals to the DSPs are connected point-to-point

between PCI2040 and each implemented DSP. The PCI2040 resets the DSPs when GRST

is asserted. It is software’s responsibility to deassert HRSTn.

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