PCI2040 datasheet(18/79 Pages) TI

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2–6

Table 2–5. Miscellaneous Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

NAME

PGE

GGU

I/O

DESCRIPTION

GRST

Global reset. This is a power-on reset to PCI2040 that indicates that a power has been applied to

the VCC terminals. GRST resets all register bits in PCI2040.

PME

N11

Power management event. This output indicates PCI power management wake-up events to the

host, and requires open-drain, fail-safe signaling per the

PCI Bus Power Management Interface

Specification.

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

130

129

127

126

125

124

I/O

General-purpose inputs/output. With some exceptions, these terminals provide basic general-

purpose input and output functionality programmable through the PCI2040.

The GPIO3 and GPIO2 inputs may be programmed to generate generic interrupt events. See

Section 3.7.4,

General-Purpose Interrupts, for details.

GPIO0 is sampled on GRST to determine if a serial ROM is implemented. If GPIO0 is sampled high

on GRST assertions, then the serial ROM clock (SCL) is routed to the GPIO0 terminal and the serial

ROM data line (SDA) is routed to the GPIO1 terminal.

GPIO4. GP write strobe. This active low signal is used to indicate a read from a device on the bus.

The data on the bus is valid on the rising edge of WR.

GPIO5. GP read strobe. This active low signal is used to indicate a write to a device on the bus. The

data on the bus is valid on the rising edge of RD.

RSVD

35, 36,

69,

131–144

A2–A5,

B2–B5,

C3–C6,

D5, D6,

M1, M2,

M11

Reserved. These terminals are not connected in PCI2040 implementations.

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