PCI2040 datasheet(26/79 Pages) TI

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3–6

3.6

General-Purpose I/O Interface

The PCI2040 has six general-purpose input/output (GPIO) terminals for design flexibility, and these terminals reside

in the VCCP signaling environment. GPIO5–GPIO0 default to inputs, but may be programmed to be outputs via the

GPIO direction control register (see Section 4.23). When GPIOx is selected as an input, the logical value of the data

input on GPIOx is reported through the GPIO input data register (see Section 4.22). When GPIOx is selected as an

output, the logical value of the data driven by PCI2040 to the GPIOx terminal is programmed via the GPIO output

data register (see Section 4.24). The GPIO input data register, GPIO output data register, and GPIO direction control

select register (see Section 4.21).

Through the GPIO select register, the GPIO5–GPIO0 terminals may be programmed to other signal functions, such

as test outputs and general-purpose interrupt event inputs. See Section 4.21,

GPIO select register, for more details

on these options.

If bit 5 in the miscellaneous control register is set to 1 (see Section 4.26), then GPIO5 and GPIO4 provide some

signals from the general-purpose bus interface. Also note that GPIO0 and GPIO1 provide the serial ROM interface

if enabled as described in Section 3.4,

Serial ROM Interface.

3.7

Interrupts

The PCI2040 reports two classes of interrupts: DSP interrupts and device interrupts. DSP interrupts are generated

when an implemented DSP asserts its HINTn signal, and device interrupts come directly from the remaining PCI2040

logic. For example, one such PCI2040 device interrupt indicates that a serious error has occurred on the HPI

interface.

3.7.1

Interrupt Event and Interrupt Mask Registers

The PCI2040 contains two 32-bit registers to report and control interrupts: interrupt event register (see Section 5.1)

and interrupt mask register (see Section 5.2). These registers exist in the HPI control and status register space. Both

registers have two addresses: a set address and a clear address. For a write to either register, a 1 written to the set

address causes the corresponding bit in the register to be set (excluding bits that are read-only), while a 1 written

to the clear address causes the corresponding bit to be cleared. For both addresses, writing a 0 has no effect on the

corresponding bit in the register.

The interrupt event register contains the actual PCI2040 interrupt request bits, and the response to these sources

can be tested by diagnostic software by setting the corresponding bit in the interrupt event set register. The interrupt

mask register is AND’ed with the interrupt event register to enable selected sources to generate host interrupts

through INTA. Software writes to the interrupt event clear register to clear interrupt conditions reported in the interrupt

event register.

Reading either the set or the clear address for these registers returns the value of the register with one exception.

Reading the interrupt event clear register returns the value of the interrupt event register AND’ed with the interrupt

mask register to report the unmasked bits that are set in the interrupt event register that caused the interrupt event.

Software can then write this value to the interrupt event clear register, which clears the events causing the interrupt,

and the PCI2040 deasserts INTA if no more unmasked interrupt events are pending.

PCI2040 also implements a global interrupt enable in the interrupt mask register at bit 31 (masterIntEnable). Only

when bit 31 is set will the PCI2040 generate an INTA.

3.7.2

DSP-to-Host Interrupts

These interrupts are the most common interrupts generated by the PCI2040. The four interrupt events,

IntDSP3–IntDSP0 (bits 3–0 in Section 5.2), occur when the corresponding HINT3–HINT0 is asserted by the DSP.

When enabled via the corresponding bits in the interrupt mask register (see Section 5.1), these DSP interrupts are

passed directly to the PCI host.

PCI2040 Datasheet(PDF) 26 Page - Texas Instruments

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