MAC7200 datasheet(444/976 Pages) FREESCALE

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PFLASH Application Usage

MAC7200 Microcontroller Family Reference Manual, Rev. 2

366

Freescale Semiconductor

Eqn. 18-1

Eqn. 18-2

with the following parameters :

•

H7fb access delay tacc = 29 ns

•

H7fb pipelined read delay trr = 18 ns

•

pflash_h7fb delay = 2 ns

•

axbs hrdata delay = 1.5 ns

•

bus master setup = 2.5 ns

•

Total Data Delay = 35 ns

•

Total Addr Delay = 24 ns

18.7.4.1.2

PFAPR - PFLASH Access Protection Register

The PFAPR register contains access protection controls. The ARM7 core is designated M0, and the DMA

is designated M1.

The reset value corresponds to the ARM7 core having read/write access, and the DMA not.

Table 18-5. Flash Controller APC and RWSC Settings

Frequency (MHz)

Period (ns)

APC

RWSC

PRD

Notes

See Note a

a. APC must be greater than or equal to RWSC at this frequency. If APC < RWSC, a pipelined read will

return data before the previous read data has been acknowledged. Therefore, the previous read will

return data from the next pipelined read

See Note a

33.33

See Note a

See Note b

b. APC must be greater than or equal to RWSC-1 at this frequency. If APC < RWSC-1, a pipelined read

will return data before the previous read data has been acknowledged. Therefore, the previous read

will return data from the next pipelined read

See Note a

16.66

See Note a

14.286

See Note b

Bits

Function

Reset

[31:4]

MxAP - Master x Access protection (not used)

$0000000

[3:2]

M1AP - DMA Access protection

[1:0]

M0AP - Core Access protection

APC

Int

Total Addr Delay

Period

--------------------------------------------

⎝⎠

⎛⎞

RWSC

Int

Total Data Delay

Period

--------------------------------------------

⎝⎠

⎛⎞

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