MAC7200 datasheet(442/976 Pages) FREESCALE

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PFLASH Application Usage

MAC7200 Microcontroller Family Reference Manual, Rev. 2

364

Freescale Semiconductor

18.7.4.1.1

PFCR1 - PFLASH Configuration Register 1

The PFCR1 register contains line buffer and pipeline controls.

The PFCR1 register may be locked (i.e.-writes are not allowed) by clearing PFCR2[23]. In the case of

any problems with the line buffers in the Flash controller (i.e.-functional bugs, etc.), the BFEN bit may be

cleared, thus disabling the buffers and associated logic.

The following table describes the allowed values for each of the fields in the PFCR1 register:

LMS

$0010

LAS/MAS Erase/Program Block Select

$0000 0000

HBS

$0014

HAS Erase/Program Block Select

$0000 0000

ADR

$0018

Aborted Address

$0000 0000

BIU0

$001c

PFCR1

(Pre-fetch control, # wait states, etc.)

$0001 4a15

BIU1

$0020

PFAPR

(Master access protection)

$0000 0007

BIU2

$0024

PFCR2

(Line Buffer Config + Shadow SACC/DACC)

From Shadow $7e00

BIU3

$0028

PFSACC (Main Array)

From Shadow $7e08

BIU4

$002c

PFDACC (Main Array)

From Shadow $7e10

Bits

Function

Reset

[31:18]

MxPFE - Master x Pre-fetch Enable (not used)

$0000

[17]

M1PFE - DMA Master Pre-fetch Enable

[16]

M0PFE - Core Master Pre-fetch Enable

[15:13]

APC - Address Pipelining Control

010

[12:11]

WWSC - Write Wait State Control

[10:8]

RWSC - Read Wait State Control

010

[7]

Reserved for future use

[6]

DPFEN - Data Prefetch Enable

[5]

Reserved for future use

[4]

IPFEN - Instruction Prefetch Enable

[3]

Reserved for future use

[2:1]

PFLIM - Prefetch Limit

[0]

BFEN - Line Read Buffer Enable

Table 18-3. Flash Block IPI User Registers

Address

Offset

Function

Reset Value

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