MAC7200 datasheet(534/976 Pages) FREESCALE

534 / 976 page

Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

456

Freescale Semiconductor

25.3.1.5

System Reset Register

The System Reset register provides a hardware interlocked method of resetting the system via software.

Table 25-9. ERROR Field Descriptions

Field

Description

PER_

ABORT

Peripheral Bus Abort Enable. This bit enables bus aborts on any access to a peripheral slot that is not used on the

device. This feature is intended to aid in debugging when developing application code.

1 Illegal accesses to non-existing peripherals produce a Prefetch or Data Abort exception

0 Illegal accesses to non-existing peripherals do not produce a Prefetch or Data Abort exception; This includes the

following address spaces:

0xFC09 C000 – 0xFC0A BFFF

0xFC0C 0000 – 0xFC0C 3FFF

0xFC0C C000 – 0xFC0D BFFF

0xFC0E 4000 – 0xFC0E 7FFF

0xFC0E C000 – 0xFC0F 0000

0xFC0F 4000 – 0xFFFF FFFF

Note: Accesses to the following address spaces will produce a Prefetch or Data Abort exception, regardless of the

value of the PER_ABORT bit:

0xFC00 C000 – 0xFC03 FFFF

0xFC04 C000 – 0xFC07 FFFF

REG_

ABORT

accesses are defined as reads or writes to reserved addresses within the address space for a particular peripheral.

This feature is intended to aid in debugging when developing application code.

1 Illegal accesses to peripherals produce a Prefetch or Data Abort exception

0 Illegal accesses to peripherals do not produce a Prefetch or Data Abort exception

This includes the following peripherals:

• SSM

• DMA Channel Mux

• CRG

• PIT_RTI

• VREG_3V3

• FLEXCAN_A/FLEXCAN_B

•IIC

• DSPI_A/DSPI_B

• SCI_A/SCI_B

• eMIOS

•ATD

• CFM (registers)

• PIM

All other modules (DMA, MCM, AEIM, etc.) are not affected by this register, and will produce Prefetch or Data Abort

exceptions for illegal accesses, regardless of the value of the REG_ABORT bit.

Note: Transfers to Peripheral Bus resources may be aborted even before they reach the Peripheral Bus (i.e. at the

AIPS level). In this case, the PER_ABORT and REG_ABORT register bits will have no effect on the abort.

Table 25-10. ERROR Allowed Register Accesses

8-bit

16-bit

32-bit

READ

Allowed

WRITE

Allowed

MAC7200 Datasheet(PDF) 534 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 534 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL