MAC7200 datasheet(582/976 Pages) FREESCALE

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FlexCAN2 Implementation on the MAC7200

MAC7200 Microcontroller Family Reference Manual, Rev. 2

504

Freescale Semiconductor

Supervisor Access: All User Mode accesses to addresses not marked with a ‘U’ are aborted.

28.1.7

CAN Differences from MAC71xx

•

Fixed MUCts01374: Message Buffer deactivation in Bus Off holds arbitration

•

Removed wakeup glitch filter (and hence wakeup on bus activity)

28.1.8

CAN Application Usage

28.1.8.1

Enabling the CAN

Before the FlexCAN can be used, it must be explicitly enabled by clearing the MDIS bit.

Table 28-2. FlexCAN Memory Map

Address Offset

Modes Allowed1

1. S

Supervisor Mode Access

User Mode Access

$0000

Module Configuration (MCR)

$0004

Control Register (CTRL)

S/U

$0008

Free Running Timer (TIMER)

S/U

$000C

Reserved

NONE

$0010

Rx Global Mask (RXGMASK)

S/U

$0014

Rx Buffer 14 Mask (RX14MASK)

S/U

$0018

Rx Buffer 15 Mask (RX15MASK)

S/U

$001C

Error Counter Register (ECR)

S/U

$0020

Error and Status Register (ESR)

S/U

$0024

Interrupt Masks 2 (IMASK2)

S/U

$0028

Interrupt Masks 1 (IMASK1)

S/U

$002C

Interrupt Flags 2 (IFLAG2)

S/U

$0030

Interrupt Flags 1 (IFLAG1)

S/U

$0034 - $005F

Reserved

NONE

$0060 - $007F

Reserved

NONE

$0080 - $017F

Message Buffers MB0 - MB15

S/U

$0180 - $027F

Message Buffers MB16 - MB31

S/U

$0280 - $3FFF

Reserved

NONE

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