MAC7200 datasheet(620/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

542

Freescale Semiconductor

Mask Registers can only be accessed in Freeze Mode, and this is still true for unused space within

this memory. Note also that reserved words within RAM cannot be used. As an example, suppose

FlexCAN is configured with 64 MBs and MAXMB is programmed with zero. The maximum

number of MBs in this case becomes one. The MB memory starts at $0060, but the space from

$0060 to $007F is reserved (for SMB usage), and the space from $0080 to $008F is used by the

one MB. This leaves us with the available space from $0090 to $047F. The available memory in

the Mask Registers space would be from $0884 to $097F.

NOTE

Unused MB space must not be used as general purpose RAM while

FlexCAN is transmitting and receiving CAN frames.

28.2.8

Initialization/Application Information

This section provide instructions for initializing the FlexCAN module.

28.2.8.1

FlexCAN Initialization Sequence

The FlexCAN module may be reset in three ways:

•

MCU level hard reset, which resets all memory mapped registers asynchronously

•

MCU level soft reset, which resets some of the memory mapped registers synchronously (refer to

Table 28-4 to see what registers are affected by soft reset)

•

SOFT_RST bit in MCR, which has the same effect as the MCU level soft reset

Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock

domains. Therefore, it may take some time to fully propagate its effects. The SOFT_RST bit remains

asserted while soft reset is pending, so software can poll this bit to know when the reset has completed.

Also, soft reset can not be applied while clocks are shut down in any of the low power modes. The low

power mode should be exited and the clocks resumed before applying soft reset.

The clock source (CLK_SRC bit) should be selected while the module is in Disable Mode. After the clock

source is selected and the module is enabled (MDIS bit negated), FlexCAN automatically goes to Freeze

Mode. In Freeze Mode, FlexCAN is un-synchronized to the CAN bus, the HALT and FRZ bits in MCR

MCR Register are set. The Tx pin is in recessive state and FlexCAN does not initiate any transmission or

reception of CAN frames. Note that the Message Buffers and the Rx Individual Mask Registers are not

affected by reset, so they are not automatically initialized.

•

For any configuration change/initialization it is required that FlexCAN is put into Freeze Mode

(see Section 28.2.7.8.1, “Freeze Mode”). The following is a generic initialization sequence

applicable to the FlexCAN module:Initialize the Module Configuration Register

— Enable the individual filtering per MB and reception queue features by setting the BCC bit

— Enable the warning interrupts by setting the WRN_EN bit

— If required, disable frame self reception by setting the SRX_DIS bit

•

Initialize the Control Register

— Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW

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