MAC7200 datasheet(619/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

541

The sensitivity to CAN bus activity can be modified by applying a low-pass filter function to the Rx CAN

input line while in Stop Mode. See the WAK_SRC bit in Section 28.2.6.3.1, “Module Configuration

the CAN bus lines. Such glitches can result from electromagnetic interference within noisy environments.

NOTE

Not all MCUs are equipped with the low-pass filter. Consult the specific

MCU documentation to determine if the low-pass filter is available and to

determine its electrical parameters.

28.2.7.9

Interrupts

The module can generate up to 70 interrupt sources (64 interrupts due to message buffers and 6 interrupts

due to Ored interrupts from MBs, Bus Off, Error, Tx Warning, Rx Warning, and Wake Up). The number

of actual sources depends on the configured number of Message Buffers.

Each one of the message buffers can be an interrupt source, if its corresponding IMASK bit is set. There

is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer

is initialized for either transmission or reception. Each of the buffers has assigned a flag bit in the IFLAG

Registers. The bit is set when the corresponding buffer completes a successful transmission/reception and

is cleared when the CPU writes it to ‘1’ (unless another interrupt is generated at the same time).

NOTE

It must be guaranteed that the CPU only clears the bit causing the current

interrupt. For this reason, bit manipulation instructions (BSET) must not be

used to clear interrupt flags. These instructions may cause accidental

clearing of interrupt flags which are set after entering the current interrupt

service routine.

A combined interrupt for all MBs is also generated by an Or of all the interrupt sources from MBs. This

interrupt gets generated when any of the MBs generates an interrupt. In this case the CPU must read the

IFLAG Registers to determine which MB caused the interrupt.

The other 4 interrupt sources (Bus Off, Error, Warning and Wake Up) generate interrupts like the MB ones,

and can be read from the Error and Status Register. The Bus Off , Error and Warning interrupt mask bits

are located in the Control Register, and the Wake-Up interrupt mask bit is located in the MCR.

28.2.7.10 Bus Interface

The CPU access to FlexCAN registers are subject to the following rules:

•

Read and write access to supervisor registers in User Mode results in access error.

•

Read and write access to unimplemented or reserved address space also results in access error. Any

access to unimplemented MB or Rx Individual Mask Register locations results in access error. Any

access to the Rx Individual Mask Register space when the BCC bit in MCR is negated results in

access error.

•

If MAXMB is programmed with a value smaller than the available number of MBs, then the

unused memory space can be used as general purpose RAM space. Note that the Rx Individual

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