MAC7200 datasheet(616/976 Pages) FREESCALE

616 / 976 page

The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

538

Freescale Semiconductor

CAN bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock frequencies

should be at least 2.

28.2.7.8

Modes of Operation Details

28.2.7.8.1

Freeze Mode

This mode is entered by asserting the HALT bit in the MCR Register or when the MCU is put into Debug

Mode. In both cases it is also necessary that the FRZ bit is asserted in the MCR Register and the module

is not in any of the low power modes (Disable, Doze, Stop). When Freeze Mode is requested during

transmission or reception, FlexCAN does the following:

•

Waits to be in either Intermission, Passive Error, Bus Off or Idle state

•

Waits for all internal activities like arbitration, matching, move-in and move-out to finish

•

Ignores the Rx input pin and drives the Tx pin as recessive

•

Stops the prescaler, thus halting all CAN protocol activities

•

Grants write access to the Error Counters Register, which is read-only in other modes

•

Sets the NOT_RDY and FRZ_ACK bits in MCR

After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in MCR before

executing any other action, otherwise FlexCAN may operate in an unpredictable way. In Freeze mode, all

memory mapped registers are accessible.

Exiting Freeze Mode is done in one of the following ways:

•

CPU negates the FRZ bit in the MCR Register

•

The MCU is removed from Debug Mode and/or the HALT bit is negated

Once out of Freeze Mode, FlexCAN tries to re-synchronize to the CAN bus by waiting for 11 consecutive

recessive bits.

28.2.7.8.2

Module Disable Mode

This low power mode is entered when the MDIS bit in the MCR Register is asserted. If the module is

disabled during Freeze Mode, it shuts down the clocks to the CPI and MBM sub-modules, sets the

LPM_ACK bit and negates the FRZ_ACK bit. If the module is disabled during transmission or reception,

FlexCAN does the following:

•

Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and then

checks it to be recessive

•

Waits for all internal activities like arbitration, matching, move-in and move-out to finish

•

Ignores its Rx input pin and drives its Tx pin as recessive

•

Shuts down the clocks to the CPI and MBM sub-modules

•

Sets the NOT_RDY and LPM_ACK bits in MCR

The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped registers, except

the Free Running Timer, the Error Counter Register and the Message Buffers, which cannot be accessed

MAC7200 Datasheet(PDF) 616 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 616 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL