MAC7200 datasheet(618/976 Pages) FREESCALE

618 / 976 page

The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

540

Freescale Semiconductor

The sensitivity to CAN bus activity can be modified by applying a low-pass filter function to the Rx CAN

input line while in Doze Mode. See the WAK_SRC bit in Section 28.2.6.3.1, “Module Configuration

the CAN bus lines. Such glitches can result from electromagnetic interference within noisy environments.

NOTE

Not all MCUs are equipped with the low-pass filter. Consult the specific

MCU documentation to determine if the low-pass filter is available, and to

determine its electrical parameters.

28.2.7.8.4

Stop Mode

This is a system low power mode in which all MCU clocks are stopped for maximum power savings. If

FlexCAN receives the global Stop Mode request during Freeze Mode, it sets the LPM_ACK bit, negates

the FRZ_ACK bit and then sends a Stop Acknowledge signal to the CPU, in order to shut down the clocks

globally. If Stop Mode is requested during transmission or reception, FlexCAN does the following:

•

Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and checks

it to be recessive

•

Waits for all internal activities like arbitration, matching, move-in and move-out to finish

•

Ignores its Rx input pin and drives its Tx pin as recessive

•

Sets the NOT_RDY and LPM_ACK bits in MCR

•

Sends a Stop Acknowledge signal to the CPU, so that it can shut down the clocks globally

Exiting Stop Mode is done in one of the following ways:

•

CPU resuming the clocks and removing the Stop Mode request

•

CPU resuming the clocks and Stop Mode request as a result of the Self Wake mechanism

In the Self Wake mechanism, if the SLF_WAK bit in MCR Register was set at the time FlexCAN entered

Stop Mode, then upon detection of a recessive to dominant transition on the CAN bus, FlexCAN sets the

WAK_INT bit in the ESR Register and, if enabled by the WAK_MSK bit in MCR, generates a Wake Up

interrupt to the CPU. Upon receiving the interrupt, the CPU should resume the clocks and remove the Stop

Mode request. FlexCAN will then wait for 11 consecutive recessive bits to synchronize to the CAN bus.

As a consequence, it will not receive the frame that woke it up. Table 28-20 details the effect of SLF_WAK

and WAK_MSK upon wake-up from Stop Mode. Note that wake-up from Stop Mode only works when

both bits are asserted.

Table 28-20. Wake-up from Stop Mode

SLF_WAK

WAK_MSK

MCU

Clocks

Enabled

Wake-up

Interrupt

Generated

Yes

MAC7200 Datasheet(PDF) 618 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 618 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL