MAC7200 datasheet(617/976 Pages) FREESCALE

617 / 976 page

The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

539

when the module is in Disable Mode. Exiting from this mode is done by negating the MDIS bit, which will

resume the clocks and negate the LPM_ACK bit.

28.2.7.8.3

Doze Mode

This is a system low power mode in which the CPU bus is kept alive and a global Doze Mode request is

sent to all peripherals asking them to enter low power mode. When Doze Mode is globally requested, the

DOZE bit in MCR needs to have been asserted previously for Doze Mode to be triggered. If Doze Mode

is triggered during Freeze Mode, FlexCAN shuts down the clocks to the CPI and MBM sub-modules, sets

the LPM_ACK bit and negates the FRZ_ACK bit. If Doze Mode is triggered during transmission or

reception, FlexCAN does the following:

•

Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and checks

it to be recessive

•

Waits for all internal activities like arbitration, matching, move-in and move-out to finish

•

Ignores its Rx input pin and drives its Tx pin as recessive

•

Shuts down the clocks to the CPI and MBM sub-modules

•

Sets the NOT_RDY and LPM_ACK bits in MCR

The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped registers, except

the Free Running Timer, the Error Counter Register and the Message Buffers, which can not be accessed

in Doze Mode.

Exiting Doze Mode is done in one of the following ways:

•

CPU removing the Doze Mode request

•

CPU negating the DOZE bit of the MCR Register

•

Self Wake mechanism

In the Self Wake mechanism, if the SLF_WAK bit in MCR Register was set at the time FlexCAN entered

Doze Mode, then upon detection of a recessive to dominant transition on the CAN bus, FlexCAN negates

the DOZE bit and resumes its clocks. It also sets the WAK_INT bit in the ESR Register and, if enabled by

the WAK_MSK bit in MCR, generates a Wake Up interrupt to the CPU. FlexCAN will then wait for 11

consecutive recessive bits to synchronize to the CAN bus. As a consequence, it will not receive the frame

that woke it up. Table 28-19 details the effect of SLF_WAK and WAK_MSK upon wake-up from Doze

Mode.

Table 28-19. Wake-up from Doze Mode

SLF_WAK

WAK_MSK

FlexCAN

Clocks

Enabled

Wake-up

Interrupt

Generated

Yes

MAC7200 Datasheet(PDF) 617 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 617 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL