MAC7200 datasheet(613/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

535

(generally from a PLL). In order to guarantee reliable operation, the clock source should be selected while

the module is in Disable Mode (bit MDIS set in the Module Configuration Register).

Figure 28-12. CAN Engine Clocking Scheme

The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the

CAN bus timing. The crystal oscillator clock has better jitter performance than PLL generated clocks.

NOTE

This clock selection feature may not be available in all MCUs. A particular

MCU may not have a PLL, in which case it would have only the oscillator

clock, or it may use only the PLL clock feeding the FlexCAN module. In

these cases, the CLK_SRC bit in the CTRL Register has no effect on the

module operation.

The FlexCAN module supports a variety of means to setup bit timing parameters that are required by the

CAN protocol. The Control Register has various fields used to control bit timing parameters: PRESDIV,

PROPSEG, PSEG1, PSEG2 and RJW. See Section 28.2.6.3.2, “Control Register (CTRL).”

The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose period defines the

‘time quantum’ used to compose the CAN waveform. A time quantum is the atomic unit of time handled

by the CAN engine.

Eqn. 28-1

A bit time is subdivided into three segments1 (reference Figure 28-13 and Table 28-16):

•

SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to

happen within this section

•

Time Segment 1: This segment includes the Propagation Segment and the Phase Segment 1 of the

CAN standard. It can be programmed by setting the PROPSEG and the PSEG1 fields of the CTRL

•

Time Segment 2: This segment represents the Phase Segment 2 of the CAN standard. It can be

programmed by setting the PSEG2 field of the CTRL Register (plus 1) to be 2 to 8 time quanta long

Eqn. 28-2

1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch

CAN 2.0A/B protocol specification dated September 1991 for bit timing.

Peripheral Clock (PLL)

Oscillator Clock (Xtal)

CLK_SRC

Prescaler

(1 .. 256)

Sclock

CPI Clock

CANCLK

Prescaler value

-----------------------------------------

Bit Rate

number of Time Quanta

---------------------------------------------------------------

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