MAC7200 datasheet(610/976 Pages) FREESCALE

610 / 976 page

The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

532

Freescale Semiconductor

Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports individual

masking per MB. Refer to Section 28.2.6.3.11, “Rx Individual Mask Registers (RXIMR0–RXIMR63).”

During the matching algorithm, if a mask bit is asserted, then the corresponding ID bit is compared. If the

mask bit is negated, the corresponding ID bit is “don’t care”. Please note that the Individual Mask

Registers are implemented in RAM, so they are not initialized out of reset. Also, they can only be

programmed if the BCC bit is asserted and while the module is in Freeze Mode.

FlexCAN also supports an alternate masking scheme with only three mask registers (RGXMASK,

RX14MASK and RX15MASK) for backwards compatibility. This alternate masking scheme is enabled

when the BCC bit in the MCR Register is negated.

NOTE

The individual Rx Mask per Message Buffer feature may not be available in

low cost MCUs. Please consult the specific MCU documentation to find out

if this feature is supported. If not supported, the RXGMASK, RX14MASK

and RX15MASK registers are available, regardless of the value of the BCC

bit.

28.2.7.6

Data Coherence

In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described

in Section 28.2.7.2, “Transmit Process,” and Section 28.2.7.4, “Receive Process.” Any form of CPU

accessing an MB structure within FlexCAN other than those specified may cause FlexCAN to behave in

an unpredictable way.

28.2.7.6.1

Message Buffer Deactivation

If the CPU wants to change the function of an active MB, the recommended procedure is to first put the

module into Freeze Mode and then change the Code field of that MB. This is a safe procedure because

FlexCAN waits for pending CAN bus and MB moving activities to finish before entering Freeze Mode.

Nevertheless, a mechanism is provided to maintain data coherence when the CPU writes to the Control

and Status word of active MBs out of Freeze Mode.

Any CPU write access to the Control and Status word of an MB causes that MB to be excluded from the

transmit or receive processes during the current matching or arbitration round. This mechanism is called

MB deactivation. It is temporary, affecting only for the current match/arbitration round.

The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to decide

which MB to transmit or receive. If the CPU updates the MB in the middle of a match or arbitration

process, the data of that MB may no longer be coherent, therefore deactivation of that MB is done.

Even with the coherence mechanism described above, writing to the Control and Status word of active

MBs when not in Freeze Mode may produce undesirable results. Examples are:

•

Matching and arbitration are one-pass processes. If MBs are deactivated after they are scanned, no

re-evaluation is done to determine a new match/winner. If an Rx MB with a matching ID is

deactivated during the matching process after it was scanned, then this MB is marked as invalid to

receive the frame, and FlexCAN will keep looking for another matching MB within the ones it has

not scanned yet. If it can not find one, then the message will be lost. Suppose, for example, that two

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