MAC7200 datasheet(611/976 Pages) FREESCALE

611 / 976 page

The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

533

MBs have a matching ID to a received frame, and the user deactivated the first matching MB after

FlexCAN has scanned the second. The received frame will be lost even if the second matching MB

was “free to receive”.

•

If a Tx MB containing the lowest ID is deactivated after FlexCAN has scanned it, then FlexCAN

will look for another winner within the MBs that it has not scanned yet. Therefore, it may transmit

an MB with ID that may not be the lowest at the time because a lower ID might be present in one

of the MBs that it had already scanned before the deactivation.

•

There is a point in time until which the deactivation of a Tx MB causes it not to be transmitted (end

of move-out). After this point, it is transmitted but no interrupt is issued and the Code field is not

updated.

28.2.7.6.2

Message Buffer Lock Mechanism

Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive process. When

the CPU reads the Control and Status word of an “active not empty” Rx MB, FlexCAN assumes that the

CPU wants to read the whole MB in an atomic operation, and thus it sets an internal lock flag for that MB.

The lock is released when the CPU reads the Free Running Timer (global unlock operation), or when it

reads the Control and Status word of another MB. The MB locking is done to prevent a new frame to be

written into the MB while the CPU is reading it.

NOTE

The locking mechanism only applies to Rx MBs which have a code different

than INACTIVE (‘0000’) or EMPTY1 (‘0100’). Also, Tx MBs can not be

locked.

Suppose, for example, that the second and the fifth MBs of the array are programmed with the same ID,

and FlexCAN has already received and stored messages into these two MBs. Suppose now that the CPU

decides to read MB number 5 and at the same time another message with the same ID is arriving. When

the CPU reads the Control and Status word of MB number 5, this MB is locked. The new message arrives

and the matching algorithm finds out that there are no “free to receive” MBs, so it decides to override MB

number 5. However, this MB is locked, so the new message can not be written there. It will remain in the

SMB waiting for the MB to be unlocked, and only then will be written to the MB. If the MB is not unlocked

in time and yet another new message with the same ID arrives, then the new message overwrites the one

on the SMB and there will be no indication of lost messages either in the Code field of the MB or in the

Error and Status Register.

While the message is being moved-in from the SMB to the MB, the BUSY bit on the Code field is asserted.

If the CPU reads the Control and Status word and finds out that the BUSY bit is set, it should defer

accessing the MB until the BUSY bit is negated.

NOTE

If the BUSY bit is asserted or if the MB is empty, then reading the Control

and Status word does not lock the MB.

1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honoured when

the BCC bit is negated.

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