MAC7200 datasheet(609/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

531

Note that the received ID field is always stored in the matching MB, thus the contents of the ID field in an

MB may change if the match was due to masking. Note also that FlexCAN does receive frames transmitted

by itself if there exists an Rx matching MB, provided the SRX_DIS bit in the MCR is not asserted. If

SRX_DIS is asserted, FlexCAN will not store frames transmitted by itselt in any MB, even if it contains

a matching MB, and no interrupt flag or interrupt signal will be generated due to the frame reception.

28.2.7.5

Matching Process

The matching process is an algorithm executed by the MBM that scans the whole MB memory looking for

Rx MBs programmed with the same ID as the one received from the CAN bus. Only MBs programmed to

receive will participate in the matching process for received frames.

While the ID, DLC and Data fields are retrieved from the CAN bus, they are stored temporarily in the

Serial Message Buffer (SMB). The matching process takes place during the CRC field. If a matching ID

is found in one of the MBs, the contents of the SMB will be transferred to the matched MB during the 6th

bit of the End-Of-Frame field of the CAN protocol. This operation is called “move-in”. If any protocol

error (CRC, ACK, etc.) is detected, than the move-in operation does not happen.

An MB with a matching ID is said to be “free to receive” a new frame if the following conditions are

satisfied:

•

The MB is not locked (see Section 28.2.7.6.2, “Message Buffer Lock Mechanism”)

•

The Code field is either EMPTY or else it is FULL or OVERRUN but the CPU has already serviced

the MB (read the C/S word and then unlocked the MB)

If the first MB with a matching ID is not “free to receive” the new frame, then the matching algorithm

keeps looking for another free MB until it finds one. If it can not find one that is free, then it will overwrite

the last matching MB (unless it is locked) and set the Code field to OVERRUN (refer to Table 28-7 and

Table 28-8). If the last matching MB is locked, then the new message remains in the SMB, waiting for the

MB to be unlocked (see Section 28.2.7.6.2, “Message Buffer Lock Mechanism”).

Suppose, for example, that there are two MBs with the same ID and FlexCAN starts receiving messages

with that ID. Let us say that these MBs are the second and the fifth in the array. When the first message

arrives, the matching algorithm will find the first match in MB number 2. The code of this MB is EMPTY,

so the message is stored there. When the second message arrives, the matching algorithm will find MB

number 2 again, but it is not “free to receive”, so it will keep looking and find MB number 5 and store the

message there. If yet another message with the same ID arrives, the matching algorithm finds out that there

are no matching MBs that are “free to receive”, so it decides to overwrite the last matched MB, which is

number 5. In doing so, it sets the Code field of the MB to indicate OVERRUN.

The ability to match the same ID in more than one MB can be exploited to implement a reception queue

to allow more time to the CPU for servicing the MBs. By programming more than one MB with the same

ID, received messages will be queued into the MBs. The CPU can examine the Time Stamp field of the

MBs to determine the order in which the messages arrived.

The matching algorithm described above can be changed to be the same one used in previous versions of

the FlexCAN module. When the BCC bit in MCR is negated, the matching algorithm stops at the first MB

with a matching ID that it founds, whether this MB is free or not. As a result, the message queueing feature

does not work if the BCC bit is negated.

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