MAC7200 datasheet(605/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

527

28.2.6.3.10

Interrupt Flags 1 Register (IFLAG1)

This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt flag bit per buffer.

Each successful transmission or reception sets the corresponding IFLAG1 bit. If the corresponding

IMASK1 bit is set, an interrupt will be generated. The Interrupt flag must be cleared by writing it to ‘1’.

Writing ‘0’ has no effect.

28.2.6.3.11

Rx Individual Mask Registers (RXIMR0–RXIMR63)

These registers are used as acceptance masks for received frame ID, in both Standard and Extended ID

formats. One mask register is provided for each Message Buffer for individual ID masking per Message

Buffer. The meaning of each mask bit is the following:

•

Mask bit = 0: the corresponding incoming ID bit is “don’t care”

•

Mask bit = 1: the corresponding ID bit is checked against the incoming ID bit, to see if a match

exists

The Individual Rx Mask Registers are implemented in RAM, so they are not affected by reset and must be

explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the

module is in Freeze Mode. Out of Freeze Mode, write accesses are blocked and read accesses will return

“all zeros”. Furthermore, if the BCC bit in the MCR Register is negated, any read or write operation to

these registers results in access error.

Address: Base + $0030

R BUF

31I

BUF

30I

BUF

29I

BUF

28I

BUF

27I

BUF

26I

BUF

25I

BUF

24I

BUF

23I

BUF

22I

BUF

21I

BUF

20I

BUF

19I

BUF

18I

BUF

17I

BUF

16I

Reset

000000000000000

9876543210

R BUF

15I

BUF

14I

BUF

13I

BUF

12I

BUF

11I

BUF

10I

BUF

Reset

000000000000000

Figure 28-10. Interrupt Flags 1 Register (IFLAG1)

Table 28-14. IFLAG1 Field Descriptions

Field

Description

31–0

BUF31I–

BUF0I

Buffer MBi Interrupt. Each bit flags the respective FlexCAN Message Buffer (MB0 to MB31) interrupt.

0 No such occurrence

1 The corresponding buffer has successfully completed transmission or reception

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