MAC7200 datasheet(602/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

524

Freescale Semiconductor

28.2.6.3.8

Error and Status Register (ESR)

This register reflects various error conditions, some general status of the device and it is the source of four

interrupts to the CPU. The reported error conditions (bits 15–10) are those that occurred since the last time

the CPU read this register. The CPU read action clears bits 15–10. Bits 9–4 are status bits.

Most bits in this register are read only, except TWRN_INT, RWRN_INT, BOFF_INT, WAK_INT and

ERR_INT, that are interrupt flags that can be cleared by writing ‘1’ to them (writing ‘0’ has no effect). See

Section 28.2.7.9, “Interrupts,” for more details.

Address: Base + $0020

00000000000000

Reset

000000000000000

9876543210

IDLE TXRX FLT_CONF

Reset

000000000000000

Figure 28-8. Error and Status Register (ESR)

Table 28-12. ESR Field Descriptions

Field

Description

31–18

Reserved, should be cleared.

TWRN_INT

Tx Warning Interrupt Flag. If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the

TX_WRN flag transition from ‘0’ to ‘1’, meaning that the Tx error counter reached 96. If the corresponding

mask bit in the Control Register (TWRN_MSK) is set, an interrupt is generated to the CPU. This bit is

cleared by writing it to ‘1’. Writing ‘0’ has no effect.

0 No such occurrence

1 The Tx error counter transition from < 96 to

≥ 96

RWRN_INT

Rx Warning Interrupt Flag. If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the

RX_WRN flag transition from ‘0’ to ‘1’, meaning that the Rx error counter reached 96. If the corresponding

mask bit in the Control Register (RWRN_MSK) is set, an interrupt is generated to the CPU. This bit is

cleared by writing it to ‘1’. Writing ‘0’ has no effect.

0 No such occurrence

1 The Rx error counter transition from < 96 to

≥ 96

BIT1_ERR

Bit1 Error. This bit indicates when an inconsistency occurs between the transmitted and the received bit

in a message.

0 No such occurrence1At least one bit sent as recessive is received as dominant

Note: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node sending

a passive error flag that detects dominant bits.

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