MAC7200 datasheet(603/976 Pages) FREESCALE

603 / 976 page

The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

525

BIT0_ERR

Bit0 Error. This bit indicates when an inconsistency occurs between the transmitted and the received bit

in a message.

0 No such occurrence

1 At least one bit sent as dominant is received as recessive

ACK_ERR

Acknowledge Error. This bit indicates that an Acknowledge Error has been detected by the transmitter

node, i.e., a dominant bit has not been detected during the ACK SLOT.

0 No such occurrence

1 An ACK error occurred since last read of this register

CRC_ERR

Cyclic Redundancy Check Error. This bit indicates that a CRC Error has been detected by the receiver

node, i.e., the calculated CRC is different from the received.

0 No such occurrence

1 A CRC error occurred since last read of this register.

FRM_ERR

Form Error. This bit indicates that a Form Error has been detected by the receiver node, i.e., a fixed-form

bit field contains at least one illegal bit.

STF_ERR

Stuffing Error. This bit indicates that a Stuffing Error has been detected.

0 No such occurrence.

1 A Stuffing Error occurred since last read of this register.

TX_WRN

TX Error Counter. This bit indicates that repetitive errors are occurring during message transmission. If

the BCC bit in MCR is asserted, then when TX_WRN changes from 0 to 1, the WRN_INT flag is set and

an interrupt request is generated if allowed by the WRN_MSK bit in CTRL. After the WRN_INT flag is set,

no further updates will happen to TX_WRN until the WRN_INT flag is cleared by the CPU (by writing ‘1’

to it).

0 No such occurrence

1 TX_Err_Counter

≥ 96

RX_WRN

Rx Error Counter. This bit indicates when repetitive errors are occurring during message reception. If the

BCC bit in MCR is asserted, then when RX_WRN changes from 0 to 1, the WRN_INT flag is set and an

interrupt request is generated if allowed by the WRN_MSK bit in CTRL. After the WRN_INT flag is set,

no further updates will happen to RX_WRN until the WRN_INT flag is cleared by the CPU (by writing ‘1’

to it).

0 No such occurrence

1 Rx_Err_Counter

≥ 96

IDLE

CAN bus IDLE state. This bit indicates when CAN bus is in IDLE state.

0 No such occurrence

1 CAN bus is now IDLE

TXRX

Current FlexCAN status (transmitting/receiving). This bit indicates if FlexCAN is transmitting or receiving

a message when the CAN bus is not in IDLE state. This bit has no meaning when IDLE is asserted.

0 FlexCAN is receiving a message (IDLE=0)

1 FlexCAN is transmitting a message (IDLE=0)

5–4

FLT_CONF

Fault Confinement State. This 2-bit field indicates the Confinement State of the FlexCAN module, as

shown in the values below. If the LOM bit in the Control Register is asserted, the FLT_CONF field will

indicate “Error Passive”. Since the Control Register is not affected by soft reset, the FLT_CONF field will

not be affected by soft reset if the LOM bit is asserted.

00 Error active

01 Error passive

1X Bus off

Reserved, should be cleared.

Table 28-12. ESR Field Descriptions (Continued)

Field

Description

MAC7200 Datasheet(PDF) 603 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 603 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL