MAC7200 datasheet(600/976 Pages) FREESCALE

600 / 976 page

The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

522

Freescale Semiconductor

28.2.6.3.5

Rx 14 Mask (RX14MASK)

This register is provided for legacy support and for low cost MCUs that do not have the individual masking

per Message Buffer feature. See Section 28.2.6.3.11, “Rx Individual Mask Registers

(RXIMR0–RXIMR63).” For MCUs supporting individual masks per MB, setting the BCC bit in MCR

causes the RX14MASK Register to have no effect on the module operation.

RX14MASK is used as acceptance mask for the Identifier in Message Buffer 14. This register has the same

structure as the Rx Global Mask Register. It must be programmed while the module is in Freeze Mode,

and must not be modified when the module is transmitting or receiving frames.

•

Address Offset: $14

•

Reset Value: $1FFF_FFFF

28.2.6.3.6

Rx 15 Mask (RX15MASK)

This register is provided for legacy support and for low cost MCUs that do not have the individual masking

per Message Buffer feature. See Section 28.2.6.3.11, “Rx Individual Mask Registers

(RXIMR0–RXIMR63).” For MCUs supporting individual masks per MB, setting the BCC bit in MCR

causes the RX15MASK Register to have no effect on the module operation.

When the BCC bit is negated, RX15MASK is used as acceptance mask for the Identifier in Message Buffer

15. This register has the same structure as the Rx Global Mask Register. It must be programmed while the

module is in Freeze Mode, and must not be modified when the module is transmitting or receiving frames.

•

Address Offset: $18

•

Reset Value: $1FFF_FFFF

28.2.6.3.7

Error Counter Register (ECR)

This register has 2 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error Counter

(Tx_Err_Counter field) and Receive Error Counter (Rx_Err_Counter field). The rules for increasing and

decreasing these counters are described in the CAN protocol and are completely implemented in the

FlexCAN module. Both counters are read only except in Freeze Mode, where they can be written by the

CPU.

Writing to the Error Counter Register while in Freeze Mode is an indirect operation. The data is first

written to an auxiliary register and then an internal request/acknowledge procedure across clock domains

is executed. All this is transparent to the user, except for the fact that the data will take some time to be

Table 28-11. RXGMASK Field Descriptions

Field

Description

31–29

Reserved, should be cleared.

28–18

MI28–MI18

Standard ID Mask Bits. These bits are the same mask bits for the Standard and Extended Formats.

17–0

MI17–MI0

Extended ID Mask Bits. These bits are used to mask comparison only in Extended Format.

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