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MAC7200 Datasheet(PDF) 596 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 596 Page - Freescale Semiconductor, Inc

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The Generic FlexCAN2 Module
MAC7200 Microcontroller Family Reference Manual, Rev. 2
518
Freescale Semiconductor
Address: Base + $0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
PRESDIV
RJW
PSEG1
PSEG2
W
Reset
000000000000000
0
15
14
13
12
11
10
9876543210
R
LPB
00
SMP
TSYN LBUF LOM
PROPSEG
W
Reset
000000000000000
0
Figure 28-4. Control Register (CTRL)
Table 28-10. CTRL Field Descriptions
Field
Description
31–24
PRESDIV
Prescaler Division Factor. This 8-bit field defines the ratio between the CPI clock frequency and the Serial
Clock (Sclock) frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset
value, the Sclock frequency is equal to the CPI clock frequency. The Maximum value of this register is
$FF, that gives a minimum Sclock frequency equal to the CPI clock frequency divided by 256. For more
information refer to Section 28.2.7.7.4, “Protocol Timing.”
Sclock frequency = CPI clock frequency / (PRESDIV + 1)
23–22
RJW
Resync Jump Width. This 2-bit field defines the maximum number of time quanta1 that a bit time can be
changed by one re-synchronization. The valid programmable values are 0–3.
Resync Jump Width = RJW + 1.
21–19
PSEG1
Phase Segment 1. This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time. The valid
programmable values are 0–7.
Phase Buffer Segment 1 = (PSEG1 + 1) x Time-Quanta.
18–16
PSEG2
Phase Segment 2. This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid
programmable values are 1–7.
Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta.
15
BOFF_MSK
Bus Off Mask. This bit provides a mask for the Bus Off Interrupt.
0 Bus Off interrupt disabled
1 Bus Off interrupt enabled
14
ERR_MSK
Error Mask. This bit provides a mask for the Error Interrupt.
0 Error interrupt disabled
1 Error interrupt enabled



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