MAC7200 datasheet(594/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

516

Freescale Semiconductor

FRZ_ACK

Freeze Mode Acknowledge. This read-only bit indicates that FlexCAN is in Freeze Mode and its prescaler

is stopped. The Freeze Mode request cannot be granted until current transmission or reception processes

have finished. Therefore the software can poll the FRZ_ACK bit to know when FlexCAN has actually

entered Freeze Mode. If Freeze Mode request is negated, then this bit is negated once the FlexCAN

prescaler is running again. If Freeze Mode is requested while FlexCAN is in any of the low power modes,

then the FRZ_ACK bit will only be set when the low power mode is exited. See Section 28.2.7.8.1, “Freeze

Mode,” for more information.

0 FlexCAN not in Freeze Mode, prescaler running

1 FlexCAN in Freeze Mode, prescaler stopped

SUPV

Supervisor Mode. This bit configures some of the FlexCAN registers to be either in Supervisor or

Unrestricted memory space. The registers affected by this bit are marked as S/U in the Access Type

column of Table 28-4. Reset value of this bit is ‘1’, so the affected registers start with Supervisor access

restrictions.

0 Affected registers are in Unrestricted memory space

1 Affected registers are in Supervisor memory space. Any access without supervisor permission

behaves as though the access was done to an unimplemented register location

SLF_WAK

Self Wake Up. This bit enables the Self Wake Up feature when FlexCAN is in Doze Mode or Stop Mode.

If this bit had been asserted by the time FlexCAN entered Doze Mode or Stop Mode, then FlexCAN will

look for a recessive to dominant transition on the bus during these modes. If a transition from recessive

to dominant is detected during Doze Mode, FlexCAN resumes its clocks and, if enabled to do so,

generates a Wake Up interrupt to the CPU. If a transition from recessive to dominant is detected during

Stop Mode, then FlexCAN generates, if enabled to do so, a Wake Up interrupt to the CPU so that it can

resume the clocks globally. This bit can not be written while the module is in Doze Mode or Stop Mode.

0 FlexCAN Self Wake Up feature is disabled

1 FlexCAN Self Wake Up feature is enabled

WRN_EN

Warning Interrupt Enable. When asserted, this bit enables the generation of the TWRN_INT and

RWRN_INT flags in the Error and Status Register. If WRN_EN is negated, the TWRN_INT and

RWRN_INT flags will always be zero, independent of the values of the error counters, and no warning

interrupt will ever be generated.

0 TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters..

1 TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to

≥ 96.

LPM_ACK

Low Power Mode Acknowledge. This read-only bit indicates that FlexCAN is either in Disable Mode, Doze

Mode or Stop Mode. Either of these low power modes can not be entered until all current transmission or

reception processes have finished, so the CPU can poll the LPM_ACK bit to know when FlexCAN has

actually entered low power mode. See Section 28.2.7.8.2, “Module Disable Mode,” Section 28.2.7.8.3,

“Doze Mode,” and Section 28.2.7.8.4, “Stop Mode,” for more information.

0 FlexCAN not in any of the low power modes

1 FlexCAN is either in Disable Mode, Doze Mode or Stop mode

WAK_SRC

Wake Up Source. This bit defines whether the integrated low-pass filter is applied to protect the Rx CAN

input from spurious wake up. See Section 28.2.7.8.3, “Doze Mode,” and Section 28.2.7.8.4, “Stop Mode,”

for more information.

0 FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.

1 FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus

Note: The integrated low-pass filter may not be available in all MCUs. In case it is not available, the

unfiltered input is always used for wake up purposes, and this bit has no effect on the FlexCAN operation.

Table 28-9. MCR Field Descriptions (Continued)

Field

Description

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