MAC7200 datasheet(593/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

515

Table 28-9. MCR Field Descriptions

Field

Description

MDIS

Module Disable. This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts

down the clocks to the CAN Protocol Interface and Message Buffer Management sub-modules. This is

the only bit in MCR not affected by soft reset. See Section 28.2.7.8.2, “Module Disable Mode,” for more

information.

0 Enable the FlexCAN module

1 Disable the FlexCAN module

FRZ

Freeze Enable. The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR Register is

set or when Debug Mode is requested at MCU level. When FRZ is asserted, FlexCAN is enabled to enter

Freeze Mode. Negation of this bit field causes FlexCAN to exit from Freeze Mode.

0 Not enabled to enter Freeze Mode

1 Enabled to enter Freeze Mode

Reserved, should be cleared.

HALT

Halt FlexCAN. Assertion of this bit puts the FlexCAN module into Freeze Mode. The CPU should clear it

after initializing the Message Buffers and Control Register. No reception or transmission is performed by

FlexCAN before this bit is cleared. While in Freeze Mode, the CPU has write access to the Error Counter

power modes. See Section 28.2.7.8.1, “Freeze Mode,” for more information.

0 No Freeze Mode request.

1 Enters Freeze Mode if the FRZ bit is asserted.

NOT_RDY

FlexCAN Not Ready. This read-only bit indicates that FlexCAN is either in Disable Mode, Doze Mode,

Stop Mode or Freeze Mode. It is negated once FlexCAN has exited these modes.

0 FlexCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode

1 FlexCAN module is either in Disable Mode, Doze Mode, Stop Mode or Freeze Mode

WAK_MSK

Wake Up Interrupt Mask. This bit enables the Wake Up Interrupt generation.

0 Wake Up Interrupt is disabled

1 Wake Up Interrupt is enabled

SOFT_RST

Soft Reset. When this bit is asserted, FlexCAN resets its internal state machines and some of the memory

mapped registers. The following registers are reset: MCR (except the MDIS bit), TIMER, ECR, ESR,

IMASK1, IMASK2, IFLAG1, IFLAG2. Configuration registers that control the interface to the CAN bus are

not affected by soft reset. The following registers are unaffected:

•CTRL

• RXIMR0–RXIMR63

• RXGMASK, RX14MASK, RX15MASK

• all Message Buffers

The SOFT_RST bit can be asserted directly by the CPU when it writes to the MCR Register, but it is also

asserted when global soft reset is requested at MCU level. Since soft reset is synchronous and has to

follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate

its effect. The SOFT_RST bit remains asserted while reset is pending, and is automatically negated when

reset completes. Therefore, software can poll this bit to know when the soft reset has completed.

Soft reset cannot be applied while clocks are shut down in any of the low power modes. The module

should be first removed from low power mode, and then soft reset can be applied.

0 No reset request

1 Resets the registers marked as “affected by soft reset” in Table 28-4

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