MAC7200 datasheet(595/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

517

28.2.6.3.2

Control Register (CTRL)

This register is defined for specific FlexCAN control features related to the CAN bus, such as bit-rate,

programmable sampling point within an Rx bit, Loop Back Mode, Listen Only Mode, Bus Off recovery

behavior and interrupt enabling (Bus-Off, Error, Warning). It also determines the Division Factor for the

clock prescaler. Most of the fields in this register should only be changed while the module is in Disable

Mode or in Freeze Mode. Exceptions are the BOFF_MSK, ERR_MSK, WRN_MSK and BOFF_REC bits,

that can be accessed at any time.

DOZE

Doze Mode Enable. This bit defines whether FlexCAN is allowed to enter low power mode when Doze

Mode is requested at MCU level. This bit is automatically reset when FlexCAN wakes up from Doze Mode

upon detecting activity on the CAN bus (self wake-up enabled).

0 FlexCAN is not enabled to enter low power mode when Doze Mode is requested

1 FlexCAN is enabled to enter low power mode when Doze Mode is requested

SRX_DIS

Self Reception Disable. This bit defines whether FlexCAN is allowed to receive frames transmitted by

itself. If this bit is asserted, frames transmitted by the module will not be stored in any MB, regardless if

the MB is programmed with an ID that matches the transmitted frame, and no interrupt flag or interrupt

signal will be generated due to the frame reception.

0 Self reception enabled

1 Self reception disabled

BCC

Backwards Compatibility Configuration. This bit is provided to support Backwards Compatibility with

previous FlexCAN versions. When this bit is negated, the following configuration is applied:

• For MCUs supporting individual Rx ID masking, this feature is disabled. Instead of individual ID

masking per MB, FlexCAN uses its previous masking scheme with RXGMASK, RX14MASK and

RX15MASK.

• The reception queue feature is disabled. Upon receiving a message, if the first MB with a matching ID

that is found is still occupied by a previous unread message, FlexCAN will not look for another matching

MB. It will override this MB with the new message and set the CODE field to ‘0110’ (overrun).

• Generation of the WRN_INT flag and the corresponding interrupt request are disabled.

Upon reset this bit is negated, allowing legacy software to work without modification.

0 Individual Rx masking, queue feature and WRN_INT generation are disabled.

1 Individual Rx masking, queue feature and WRN_INT generation are enabled.

15–6

Reserved, should be cleared.

5–0

MAXMB

Maximum Number of Message Buffers. This 6-bit field defines the maximum number of message buffers

that will take part in the matching and arbitration processes. The reset value ($0F) is equivalent to 16 MB

configuration. This field should be changed only while the module is in Freeze Mode.

Maximum MBs in use = MAXMB + 1.

Note: MAXMB has to be programmed with a value smaller or equal to the number of available Message

Buffers, otherwise FlexCAN will not transmit or receive frames.

Table 28-9. MCR Field Descriptions (Continued)

Field

Description

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