MAC7200 datasheet(597/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

519

CLK_SRC

CAN Engine Clock Source. This bit selects the clock source to the CAN Protocol Interface (CPI) to be

either the peripheral clock (driven by the PLL) or the crystal oscillator clock. The selected clock is the one

fed to the prescaler to generate the Serial Clock (Sclock). In order to guarantee reliable operation, this bit

should only be changed while the module is in Disable Mode. See Section 28.2.7.7.4, “Protocol Timing,”

for more information.

0 The CAN engine clock source is the oscillator clock1The CAN engine clock source is the bus clock

Note: This clock selection feature may not be available in all MCUs. A particular MCU may not have a

PLL, in which case it would have only the oscillator clock, or it may use only the PLL clock feeding the

FlexCAN module. In these cases, this bit has no effect on the module operation.

LPB

Loop Back. This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs

an internal loop back that can be used for self test operation. The bit stream output of the transmitter is

fed back internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to

the recessive state (logic ‘1’). FlexCAN behaves as it normally does when transmitting, and treats its own

transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the bit

sent during the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit to

ensure proper reception of its own message. Both transmit and receive interrupts are generated.

0 Loop Back disabled

1 Loop Back enabled

TWRN_MSK

Tx Warning Interrupt Mask. This bit provides a mask for the Tx Warning Interrupt associated with the

TWRN_INT flag in the Error and Status Register. This bit has no effect if the WRN_EN bit in MCR is

negated, and it is read as zero when WRN_EN is negated.

0 Tx Warning Interrupt disabled

1 Warning Interrupt enabled

RWRN_MSK

Rx Warning Interrupt Mask. This bit provides a mask for the Rx Warning Interrupt associated with the

RWRN_INT flag in the Error and Status Register. This bit has no effect if the WRN_EN bit in MCR is

negated, and it is read as zero when WRN_EN is negated.

0 Rx Warning Interrupt disabled

1 Rx Warning Interrupt enabled

9–8

Reserved, should be cleared.

SMP

Sampling Mode. This bit defines the sampling mode of CAN bits at the Rx input.

0 Just one sample is used to determine the bit value

1 Three samples are used to determine the value of the received bit: the regular one (sample point) and

2 preceding samples, a majority rule is used

BOFF_REC

Bus Off Recovery Mode. This bit defines how FlexCAN recovers from Bus Off state. If this bit is negated,

automatic recovering from Bus Off state occurs according to the CAN Specification 2.0B. If the bit is

asserted, automatic recovering from Bus Off is disabled and the module remains in Bus Off state until the

bit is negated by the user. If the negation occurs before 128 sequences of 11 recessive bits are detected

on the CAN bus, then Bus Off recovery happens as if the BOFF_REC bit had never been asserted. If the

negation occurs after 128 sequences of 11 recessive bits occurred, then FlexCAN will re-synchronize to

the bus by waiting for 11 recessive bits before joining the bus. After negation, the BOFF_REC bit can be

re-asserted again during Bus Off, but it will only be effective the next time the module enters Bus Off. If

BOFF_REC was negated when the module entered Bus Off, asserting it during Bus Off will not be

effective for the current Bus Off recovery.

0 Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B

1 Automatic recovering from Bus Off state disabled

Table 28-10. CTRL Field Descriptions (Continued)

Field

Description

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