MAC7200 datasheet(601/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

523

actually written to the register. If desired, software can poll the register to discover when the data was

actually written.

FlexCAN responds to any bus state as described in the protocol, e.g. transmit ‘Error Active’ or ‘Error

Passive’ flag, delay its transmission start time (‘Error Passive’) and avoid any influence on the bus when

in ‘Bus Off’ state. The following are the basic rules for FlexCAN bus state transitions.

•

If the value of Tx_Err_Counter or Rx_Err_Counter increases to be greater than or equal to 128, the

FLT_CONF field in the Error and Status Register is updated to reflect ‘Error Passive’ state.

•

If the FlexCAN state is ‘Error Passive’, and either Tx_Err_Counter or Rx_Err_Counter decrements

to a value less than or equal to 127 while the other already satisfies this condition, the FLT_CONF

field in the Error and Status Register is updated to reflect ‘Error Active’ state.

•

If the value of Tx_Err_Counter increases to be greater than 255, the FLT_CONF field in the Error

and Status Register is updated to reflect ‘Bus Off’ state, and an interrupt may be issued. The value

of Tx_Err_Counter is then reset to zero.

•

If FlexCAN is in ‘Bus Off’ state, then Tx_Err_Counter is cascaded together with another internal

counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,

Tx_Err_Counter is reset to zero and counts in a manner where the internal counter counts 11 such

bits and then wraps around while incrementing the Tx_Err_Counter. When Tx_Err_Counter

reaches the value of 128, the FLT_CONF field in the Error and Status Register is updated to be

‘Error Active’ and both error counters are reset to zero. At any instance of dominant bit following

a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without

affecting the Tx_Err_Counter value.

•

If during system start-up, only one node is operating, then its Tx_Err_Counter increases in each

message it is trying to transmit, as a result of acknowledge errors (indicated by the ACK_ERR bit

in the Error and Status Register). After the transition to ‘Error Passive’ state, the Tx_Err_Counter

does not increment anymore by acknowledge errors. Therefore the device never goes to the ‘Bus

Off’ state.

•

If the Rx_Err_Counter increases to a value greater than 127, it is not incremented further, even if

more errors are detected while being a receiver. At the next successful message reception, the

counter is set to a value between 119 and 127 to resume to ‘Error Active’ state.

Address: Base + $001C

000000000000000

Reset

000000000000000

9876543210

Rx_Err_Counter

Tx_Err_Counter

Reset

000000000000000

Figure 28-7. Error Counter Register (ECR)

MAC7200 Datasheet(PDF) 601 Page - Freescale Semiconductor, Inc

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