 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MAC7200 Datasheet(PDF) 604 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MAC7200 Datasheet(HTML) 604 Page - Freescale Semiconductor, Inc |
|
|
604 / 976 page  The Generic FlexCAN2 Module MAC7200 Microcontroller Family Reference Manual, Rev. 2 526 Freescale Semiconductor 28.2.6.3.9 Interrupt Masks 1 Register (IMASK1) This register allows to enable or disable any number of a range of 32 Message Buffer Interrupts. It contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an interrupt after a successful transmission or reception (i.e., when the corresponding IFLAG1 bit is set). 2 BOFF_INT ‘Bus Off’ Interrupt. This bit is set when FlexCAN enters ‘Bus Off’ state. If the corresponding mask bit in the Control Register (BOFF_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’. Writing ‘0’ has no effect. 0 No such occurrence 1 FlexCAN module entered ‘Bus Off’ state 1 ERR_INT Error Interrupt. This bit indicates that at least one of the Error Bits (bits 15-10) is set. If the corresponding mask bit in the Control Register (ERR_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’.Writing ‘0’ has no effect. 0 No such occurrence 1 Indicates setting of any Error Bit in the Error and Status Register 0 WAK_INT Wake-Up Interrupt. When FlexCAN is in Doze Mode or Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’. Writing ‘0’ has no effect. 0 No such occurrence 1 Indicates a recessive to dominant transition received on the CAN bus when the FlexCAN module is in Doze Mode or Stop Mode Address: Base + $0028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BUF 31M BUF 30M BUF 29M BUF 28M BUF 27M BUF 26M BUF 25M BUF 24M BUF 23M BUF 22M BUF 21M BUF 20M BUF 19M BUF 18M BUF 17M BUF 16M W Reset 000000000000000 0 15 14 13 12 11 10 9876543210 R BUF 15M BUF 14M BUF 13M BUF 12M BUF 11M BUF 10M BUF 9M BUF 8M BUF 7M BUF 6M BUF 5M BUF 4M BUF 3M BUF 2M BUF 1M BUF 0M W Reset 000000000000000 0 Figure 28-9. Interrupt Masks 1 Register (IMASK1) Table 28-13. IMASK1 Field Descriptions Field Description 31–0 BUF31M– BUF0M Buffer MBi Mask. Each bit enables or disables the respective FlexCAN Message Buffer (MB0 to MB31) Interrupt. 0 The corresponding buffer Interrupt is disabled1The corresponding buffer Interrupt is enabled Note: Setting or clearing a bit in the IMASK1 Register can assert or negate an interrupt request, if the corresponding IFLAG1 bit is set. Table 28-12. ESR Field Descriptions (Continued) Field Description |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
