MAC7200 datasheet(608/976 Pages) FREESCALE

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The Generic FlexCAN2 Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

530

Freescale Semiconductor

is transmitted according to the CAN protocol rules. FlexCAN transmits up to eight data bytes, even if the

DLC (Data Length Code) value is bigger.

28.2.7.4

Receive Process

To be able to receive CAN frames, the CPU must prepare one or more Message Buffers for reception by

executing the following steps:

•

Write ‘0000’ to the Code field of the Control and Status word to keep the MB inactive

•

Write the ID word

•

Write ‘0100’ to the Code field of the Control and Status word to activate the MB

The first and last steps are mandatory. The first write to the Control and Status word is important in case

there was a pending reception or transmission. The write operation immediately deactivates the MB,

removing it from any currently ongoing arbitration or matching process, giving time for the CPU to

program the rest of the MB (see Section 28.2.7.6.1, “Message Buffer Deactivation”). Once the MB is

activated in the third step, it will be able to receive CAN frames that match the programmed ID. At the end

of a successful reception, the MB is updated by the MBM as follows:

•

The value of the Free Running Timer is written into the Time Stamp field

•

The received ID, Data (8 bytes at most) and Length fields are stored

•

The Code field in the Control and Status word is updated (see Table 28-7 and Table 28-8 in Section

Section 28.2.6.2, “Message Buffer Structure”)

•

A status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the

corresponding Interrupt Mask Register bit

Upon receiving the MB interrupt, the CPU should service the received frame using the following

procedure:

•

Read the Control and Status word (mandatory – activates an internal lock for this buffer)

•

Read the ID field (optional – needed only if a mask was used)

•

Read the Data field

•

Read the Free Running Timer (optional – releases the internal lock)

Upon reading the Control and Status word, if the BUSY bit is set in the Code field, then the CPU should

defer the access to the MB until this bit is negated. Reading the Free Running Timer is not mandatory. If

not executed the MB remains locked, unless the CPU reads the C/S word of another MB. Note that only a

single MB is locked at a time. The only mandatory CPU read operation is the one on the Control and Status

word to assure data coherency (see Section 28.2.7.6, “Data Coherence”).

The CPU should synchronize to frame reception by the status flag bit for the specific MB in one of the

IFLAG Registers and not by the Code field of that MB. Polling the Code field does not work because once

a frame was received and the CPU services the MB (by reading the C/S word followed by unlocking the

MB), the Code field will not return to EMPTY. It will remain FULL, as explained in Table 28-7. If the

CPU tries to workaround this behavior by writing to the C/S word to force an EMPTY code after reading

the MB, the MB is actually deactivated from any currently ongoing matching process. As a result, a newly

received frame matching the ID of that MB may be lost. In summary: never do polling by reading directly

the C/S word of the MBs. Instead, read the IFLAG registers.

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