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MAC7200 Datasheet(PDF) 606 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 606 Page - Freescale Semiconductor, Inc |
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606 / 976 page ![]() The Generic FlexCAN2 Module MAC7200 Microcontroller Family Reference Manual, Rev. 2 528 Freescale Semiconductor NOTE The individual Rx Mask per Message Buffer feature may not be available in low cost MCUs. Please consult the specific MCU documentation to find out if this feature is supported. If not supported, the RXGMASK, RX14MASK and RX15MASK registers are available, regardless of the value of the BCC bit. 28.2.7 Functional Description 28.2.7.1 Overview The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and receiving CAN frames. The mailbox system is composed by a set of up to 64 Message Buffers (MB) that store configuration and control data, time stamp, message ID and data (see Section 28.2.6.2, “Message Buffer Structure”). Any MB can be work as a transmission or reception buffer. An arbitration algorithm decides the prioritization of MBs to be transmitted based on either the message ID or the MB ordering. A matching algorithm makes it possible to store received frames only into MBs that have the same ID programmed on its ID field. A masking scheme makes it possible to match the ID programmed on the MB with a range of IDs on received CAN frames. A reception queue can be implemented by programming the same ID on more than one receiving MB. Data coherency mechanisms are implemented to guarantee data integrity during MB manipulation by the CPU. Before proceeding with the functional description, an important concept must be explained. A Message Buffer is said to be “active” at a given time if it can participate in the matching and arbitration algorithms that are happening at that time. An Rx MB with a ‘0000’ code is inactive (refer to Table 28-7). Similarly, a Tx MB with a ‘1000’ code is also inactive (refer to Table 28-8). An MB not programmed with either ‘0000’ or ‘1000’ will be temporarily deactivated (will not participate in the current arbitration/matching Address: Base + $0880–$097F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 15 14 13 12 11 10 9876543210 MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0 Figure 28-11. Rx Individual Mask Registers (RXIMR0–RXIMR63) Table 28-15. RXIMRn Field Descriptions Field Description 31–29 Reserved. 28–18 MI28–MI18 Standard ID Mask Bits. These bits are the same mask bits for the Standard and Extended Formats. 17–0 MI17–MI0 Extended ID Mask Bits. These bits are used to mask comparison only in Extended Format. |
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