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MAC7200 Datasheet(PDF) 621 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 621 Page - Freescale Semiconductor, Inc |
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621 / 976 page ![]() The Generic FlexCAN2 Module MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 543 — Determine the bit rate by programming the PRESDIV field — Determine the internal arbitration mode (LBUF bit) • Initialize the Message Buffers — The Control and Status word of all Message Buffers must be initialized — Other entries in each Message Buffer should be initialized as required • Initialize the Rx Individual Mask Registers • Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in CTRL Register (for Bus Off and Error interrupts) and in MCR Register for Wake-Up interrupt • Negate the HALT bit in MCR Starting with the last event, FlexCAN attempts to synchronize to the CAN bus. 28.2.8.2 FlexCAN Addressing The user can program the maximum number of MBs that will take part in the matching and arbitration processes using the MAXMB field in the MCR Register. On the MAC72xx, with its 32 Message Buffer configuration, MAXMB can be any number between 0–31. |
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