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MAC7200 Datasheet(PDF) 733 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 733 Page - Freescale Semiconductor, Inc |
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733 / 976 page ![]() Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 655 31.10.4.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the Tx output signal becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the Tx output signal. Setting TE after the stop bit appears on Tx output signal causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register. 31.10.4.5 Standard Bit Error Detection Standard Bit Error Detection implements the Bit Error Detection algorithm that is normally used by a software implementation of the LIN protocol. During a transmit frame or while the header of a RX frame is sent, it reads the received byte and compares it to the one which was sent out. If there are any mismatches between the 8 transmitted databits and the 8 received databits, the BERR flag will be set. 31.10.4.6 Fast Bit Error Detection in LIN mode Fast Bit Error Detection has been designed to allow flagging of LIN bit errors while they occur, rather than flagging them after a byte transmission has completed (see Figure 31-24). Figure 31-24. Fast Bit Error Detection on a LIN Bus TXD Pin RXD Pin LIN Physical Interface Synchronizer Stage Bus Clock Receive Shift Register Transmit Shift Register LIN Bus Compare Sample Point Bit Error |
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