MAC7200 datasheet(732/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

654

Freescale Semiconductor

the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least

significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit

position.

Hardware supports odd or even parity. When parity is enabled, the most significant bit (msb) of the data

character is the parity bit.

The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI

data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data

control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request.

When the transmit shift register is not transmitting a frame, the Tx output signal goes to the idle condition,

logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable

signal goes low and the transmit signal goes idle.

If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register

continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE

to go high after the last frame before clearing TE.

To separate messages with preambles with minimum idle line time, use this sequence between messages:

1. Write the last byte of the first message to SCIDRH/L.

2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift

3. Queue a preamble by clearing and then setting the TE bit.

4. Write the first byte of the second message to SCIDRH/L.

31.10.4.3 Break Characters

Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift

Break character length depends on the M bit in the SCI control register 1 (SCICR1) and on the BRK13 bit

in the SCI control register 3 (SCICR3). As long as SBK is at logic 1, transmitter logic continuously loads

break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes

transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the

end of a break character guarantees the recognition of the start bit of the next frame.

The eSCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a

logic 0 where the stop bit should be. Receiving a break character has these effects on eSCI registers:

•

Sets the framing error flag, FE

•

Sets the receive data register full flag, RDRF

•

Clears the SCI data registers (SCIDRH/L)

•

May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF

(see Section 31.9.2.7, “SCI Status Register 1,” and Section 31.9.2.8, “SCI Status Register 2.”)

MAC7200 Datasheet(PDF) 732 Page - Freescale Semiconductor, Inc