MAC7200 datasheet(736/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

658

Freescale Semiconductor

31.10.5.3 Data Sampling

The receiver samples the Rx input signal at the RT clock rate. The RT clock is an internal signal with a

frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 31-27) is

re-synchronized:

•

After every start bit

•

After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit

samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and

RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic

1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.

Figure 31-27. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.

Table 31-24 summarizes the results of the start bit verification samples.

If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.

To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and

RT10. Table 31-25 summarizes the results of the data bit samples.

Table 31-24. Start Bit Verification

RT3, RT5, and RT7 Samples

Start Bit Verification

Noise Flag

000

Yes

001

Yes

010

Yes

011

100

Yes

101

110

111

RESET RT CLOCK

SAMPLES

RT CLOCK

RT CLOCK COUNT

START BIT

Rx Input Signal

START BIT

QUALIFICATION

START BIT

DATA

SAMPLING

LSB

VERIFICATION

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