MAC7200 datasheet(734/976 Pages) FREESCALE

734 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

656

Freescale Semiconductor

If fast bit error detection is enabled (FBR = 1) the eSCI will compare the transmitted and the received data

stream while the transmitter is active (not idle). Once a mismatch between the transmitted data and the

received data is detected the following actions are performed:

•

The bit error flag BERR will be set

•

if SBSTP is 0 the remainder of the byte will be transmitted normally

•

if SBSTP is 1 the remaining bits in the byte after the error bit are transmitted as 1s (idle)

To adjust to different bus loads the sample point at which the incomming bit is compared to the one which

was transmitted can be selected with the BESM13 bit (see Figure 31-25). If set the comparison will be

performed at RT clock 13, otherwise at RT clock 9 (also see section Section 31.10.5.3, “Data Sampling).

Figure 31-25. Timing Diagram Fast Bit Error Detection

NOTE

To calculate the exact position of the sample point with regard to the RX pin,

the delays through the pads and the two Bus Clock cycle delay through the

input synchronizer also needs to be taken into account.

Output Transmit

Shift Register

123456789

10 11 12 13 14 15 16

Input Receive

Shift Register

BESM13 = 0

BESM13 = 1

Compare Sample Points

MAC7200 Datasheet(PDF) 734 Page - Freescale Semiconductor, Inc