MAC7200 datasheet(735/976 Pages) FREESCALE

735 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

657

31.10.5 Receiver

Figure 31-26. eSCI Receiver Block Diagram

31.10.5.1 Receiver Character Length

The eSCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI

control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in

SCI data register high (SCIDRH) is the ninth bit (bit 8).

31.10.5.2 Character Reception

During an SCI reception, the receive shift register shifts a frame in from the Rx input signal. The SCI data

After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the

SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,

indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register

2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.

If the RE bit is cleared the current frame is discarded, no receive flags will be set.

WAKE

ILT

876543210L

11-BIT RECEIVE SHIFT REGISTER

DATA

WAKEUP

PARITY

CHECKING

SCI DATA REGISTER

RIE

ILIE

RWU

RDRF

INTERNAL BUS

BUS

IDLE INTERRUPT REQUEST

RDRF/OR INTERRUPT REQUEST

SBR12–SBR0

BAUD DIVIDER

LOOP

RSRC

ROM TXD

CLOCK

IDLE

RAF

RECOVERY

CONTROL

LOGIC

LOOPS

RXD

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