MAC7200 datasheet(747/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

669

31.10.9.3 TDRE Description

The TDRE interrupt is set high by the eSCI when the transmit shift register receives a byte from the SCI

data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a

new byte can be written to the SCIDRH/L for transmission. Clear TDRE by writing it with 1.

31.10.9.4 TC Description

The TC interrupt is set by the eSCI when a transmission has been completed.A TC interrupt indicates that

there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or

break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by

writing it with 1.

31.10.9.5 RDRF Description

The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A

RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the

byte can now be read by the MCU. The RDRF interrupt is cleared by writing it with 1.

31.10.9.6 PF Description

The interrupt is set when the parity of the received data is not correct. PF is cleared by writing it with 1.

31.10.9.7 FE Description

The interrupt is set when the stop bit is read as a 0 - which violates the SCI protocol. FE is cleared by

writing it with 1.

31.10.9.8 NF Description

The NF interrupt is set when the eSCI detects noise on the receiver input. NF is cleared by writing it with 1.

31.10.9.9 OR Description

The OR interrupt is set when software fails to read the SCI data register before the receive shift register

receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data

already in the SCI data registers is not affected. The OR interrupt is cleared by writing it with 1.

31.10.9.10 IDLE Description

The IDLE interrupt is set when 10 consecutive logic 1s (if M=0) or 11 consecutive logic 1s (if M=1) appear

on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle

condition can set the IDLE flag. Clear IDLE by reading by writing it with 1.

31.10.9.11 BERR Description

The BERR flag is set when the eSCI is in LIN mode, and at least one bit in the last byte that which was

transmitted, is not read back with the same value. The flag is cleared by writing it with 1.

MAC7200 Datasheet(PDF) 747 Page - Freescale Semiconductor, Inc