MAC7200 datasheet(751/976 Pages) FREESCALE

751 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

673

Figure 31-39. DMA transfer of a TX frame

31.10.11.2 Generating an RX frame

For RX frames the header information will still be provided by the LIN master - the data, CRC and

checksum bytes (as enabled) will be provided by the LIN slave. The LIN master will verify CRC and

checksum bytes transmitted by the slave.

For an RX frame the control information needs to be written to the TX register in the same manner as for

the TX frames. Additionally the timeout bits need to be written, to define the time to complete the entire

frame. Afterwards the RXRDY bit needs to be checked (either with an interrupt, RX DMA interface, or

by polling) to detect the incoming data bytes. The checksum byte will normally not appear in the RX

Two DMA channels can be used when executing an RX frame - one to transfer the header/control

information from a memory location to the TX register, and one to transfer the incoming data bytes from

the RX register to a table in memory (see Figure 31-40). After the last byte has been stored, the DMA

controller can indicate completion to the CPU.

It is also possible to setup a whole sequence of RX and TX frames, and generate a single event at the end

of that sequence.

Break

Sync

Data

CSum

. . .

Memory

DMA

Controller

LIN SCI

TX Register

Length

Control

Data n

Data 1

TX DMA

LIN Frame

channel

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