MAC7200 datasheet(748/976 Pages) FREESCALE

748 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

670

Freescale Semiconductor

31.10.9.12 RXRDY Description

The RXRDY flag is set, when the eSCI is in LIN mode, and has received a valid data byte in an RX frame.

This will not be set for bytes which the receiver obtains by reading back the data which the LIN FSM has

sent out. The flag is cleared by writing it with 1.

31.10.9.13 TXRDY Description

The TXRDY flag is set, when the eSCI is in LIN mode, and can accept a control or data byte. The flag is

cleared by writing it with 1.

31.10.9.14 LWAKE Description

The LWAKE flag is set when the LIN hardware has detected a wakeup character, sent out by one of the

LIN slaves. This should only occur when the LIN bus is in sleep mode. The flag can be cleared by writing

it with 1.

31.10.9.15 STO Description

The STO flag is set during an RX frame, when the LIN slave has not transmitted all requested data bytes,

before the specified timeout period. The flag can be cleared by writing it with 1.

31.10.9.16 PBERR Description

If the RX input remains stuck at a fixed value for 15 cycles after a transmission has started, the LIN

hardware will set the PBERR (Physical Bus Error) flag. The flag can be cleared by writing it with 1.

31.10.9.17 CERR Description

If an RX frame had the CRC checking flag set and the two CRC bytes did not match the calculated CRC

pattern, the CERR (CRC Error) flag will be set. The flag can be cleared by writing it with 1.

31.10.9.18 CKERR Description

If an RX frame had the Checksum checking flag set (that should normally always be the case) and the last

byte did not match the calculated checksum, the CKERR (Checksum Error) flag will be set. The flag can

be cleared by writing it with 1.

31.10.9.19 FRC Description

The FRC (Frame Complete) Flag will be set after the last byte of a TX frame has been sent out, or after

the last byte of an RX frame has been received (normally that means that the checksum has been compared

to the expected value, too). This can be used to indicate to the CPU that the next frame can be set up,

however it should be noted that this might be raised before the DMA controller has transferred the last byte

from the eSCI to the memory. If the intent is to process the data, the appropriate interrupt of the DMA

controller should be used instead. The flag can be cleared by writing it with 1.

MAC7200 Datasheet(PDF) 748 Page - Freescale Semiconductor, Inc