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MAC7200 Datasheet(PDF) 754 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 754 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
676
Freescale Semiconductor
slaves are ready to receive frames (for the exact definitions please refer to section 5 - Network Management
in the LIN 2.0 specification).
31.10.11.6 System Wakeup on LIN Bus Activity
It may be desirable to generate a wakeup interrupt to the system, when a LIN wakeup character is received.
This can be implemented by switching the RXD-SCI receive pin into GPIO mode and setting up the GPIO
interrupt appropriately so that it can create wakeup interrupts, before entering STOP mode. The length of
the wakeup pulse needs to conform to the requirements specified for the GPIO interrupt. LIN 2.0
compliant wakeups should fulfill these requirements.
Alternatively an additional pin can be dedicated just for the wakeup interrupt. This pin would be brought
into GPIO mode, and externally connected to the RXD-SCI receive pin.
31.10.11.7 LIN Setup
Since the eSCI is for general purpose, some of the settings are not applicable for LIN operation. The
following setup should apply for all applications, regardless which kind of LIN slave is addressed:
a) The module needs to be enabled by writing the MDIS bit to 0
b) Both Transmitter and Receiver need to be enabled (TE=1, RE=1)
c) The data format bit M, needs to be set to 0 (8 data bits), the parity needs to be disabled (PE=0)
d) TIE, TCIE, RIE interrupt enable bits should be inactive, instead the LIN interrupts should be
used
e) The eSCI needs to be switched into LIN mode (LIN=1)
f) The LIN standard requires that the break character always be 13 bits long (BRK13=1)
g) Normally Bit Errors should cause the LIN FSM to reset, stop driving the bus immediately and
stop further DMA requests until the BERR flag has been cleared, so LDBG=0, SBSTP=1 and
BSTP=1 should be set
h) Fast Bit Error Detection provides superior Error Checking, so FBR should be set, normally it
will be used with BESM13=1
i) If available a pulldown should be enabled on the RX input
j) The error indicators NF, FE, BERR, STO, PBERR, CERR, CKERR and OVFL should be
enabled
k) Initially a wakeup character may need to be transmitted on the LIN bus, so that the LIN slaves
activate
Other settings like baud rate, DMA interface etc will depend on the LIN slaves to which the eSCI is
connected and on the desired operation of the eSCI.



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