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MAC7200 Datasheet(PDF) 829 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 829 Page - Freescale Semiconductor, Inc

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Memory Map and Register Definition
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
751
NOTE
Writing to this register will stop the current conversion and discard the
command word in ATDCW. A DMA-request for fetching a command word
will be asserted. The DMA-request for saving a result will remain as it is. A
new conversion will start after a command word has been written to the
command register.
33.10.2.5 ATD Calibration Register (ATDCAL)
This register contains the calibration constants used to adjust the ATD conversion results to reduce the total
unadjusted error. Section 33.12.2, “ATD Calibration / Result Adjustment,” for details about the calibration
scheme.
5–4
DEBUG
Debug mode support. Allows the user to enable Debug features. This is useful for debugging real-time systems,
where continuation of the conversion process after the MCU has been halted could result in abnormal system
behavior. The ATD can react in different ways when Debug mode is entered:
00 Continue conversion (Debug mode disabled for the ATD).
01 Reserved for future use.
10 Finish current conversion, then freeze.
11 Freeze immediately.
3
PRED
Pre-discharge. This bit allows to pre-discharge the sample capacitor before the actual conversion starts. The voltage
after pre-discharging is VRL. Enabling this feature will require a higher conversion time. Section 33.11.6, “Conversion
Timing and See 33.11.7 Conversions Using Predischarge for details.
0 Pre-discharge to VRL is disabled
1 Pre-discharge to VRL is enabled
2
WARP
Warp transfer curve. This bit allows to slightly warp the ATD transfer curve. This will change the raw result value of
the conversions. This bit can be used to increase the ATD accuracy (See 33.12.2 ATD Calibration / Result
Adjustment for details).
0 Warp disabled
1 Warp enabled
1–0
Reserved, should be cleared.
Address Base + 0x4
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
GCC
W
Reset
010
00
000
00
000
00
0
15
14
13
12
11
10
9
876
54
321
0
R
0
0
OCC
W
Reset
000
00
000
00
000
00
0
Figure 33-6. 32ATD Calibration Register (ATDCAL)
Table 33-10. ATDMODE Field Descriptions (Continued)
Field
Description



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