MAC7200 datasheet(827/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

749

The following formula shows how the ATD clock is derived from the system clock:

Eqn. 33-3

Example 33-1.

The system clock is assumed to be 48 MHz. As the ATD clock must be 12 MHz and below the clock

prescaler is calculated to be 48.0 MHz

/12.0 MHz = 4 resulting to 12 Mhz for ATD clock. The binary value

for a prescaler of 4 according to Table 33-9 is 0b0000_0011.

Example 33-2.

The system clock is assumed to be 50 MHz. As the ATD clock must be 12 MHz and below the clock

prescaler is calculated to be 50 MHz/12 MHz = 4.17. In this case the next possible number for a prescaler

is 5 resulting to 10.0 MHz for ATD clock. The binary value for a prescaler of 5 is 0b0000_0100.

Table 33-9 lists the various clock divider values.

Address Base + 0x02

Access: User read/write

321

PRES

Reset

000

001

Figure 33-4. ATD Prescaler Register (ATDPRE)

Table 33-8. ATDPRE Field Descriptions

Field

Description

7–0

PRES

Defines the division ratio of the system clock and therefore the rate of the ATD clock. PRES can range from 0 to 255

offering a division of the system clock from divide by 2 to divide by 256.

Table 33-9. Selection Table for System Clock Divider

PRES

[7:0]

sys clk

divide

ratio

PRES

[7:0]

sys clk

divide

ratio

0b0000_0000

not programmable 0b1111_1010

251

0b0000_0001

0b1111_1011

252

0b0000_0010

0b1111_1100

253

0b0000_0011

0b1111_1101

254

0b0000_0100

0b1111_1110

255

...

0b1111_1111

256

ATDClock

SystemClock

PRES

()

--------------------------------

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